Cloud-based video analytics services have been widely employed to support various real-world surveillance and monitoring applications while bearing the risk of disclosing sensitive visuals. The state-of-the-art (SoTA) solution has explored the feasibility of applying cryptographic techniques for privacy-preserving video analytics, but unfortunately incurs high computation and communication burdens on the end users. In this article, we propose Pri3D , an efficient privacy-preserving video analytics system performed over two distributed clouds. Pri3D flexibly combines additive and multiplicative secret sharing techniques to free end devices and facilitate on-premise analytics services. Particularly, targeting the mainstream 3D convolutional neural network (CNN) pipeline, Pri3D securely accomplishes the non-linear operations (e.g., ReLU and max pooling) in merely two interaction rounds, owing to the novel design of the bi-directional transforming protocols for different modalities of secret sharing. To further optimize the latency and bandwidth confronted with large amounts of video data, \(\textsf{AS2MS}^{++}\) and \(\textsf{MS2AS}^{++}\) are proposed by subtly utilizing randomization factors and pre-encrypted nonce. With the transforming protocols, a series of privacy-preserving layer protocols are devised and tailored to build up the privacy-preserving analytics pipeline. Theoretical analysis shows that Pri3D can effectively fulfill the desired privacy requirements. Extensive evaluations demonstrate that Pri3D provides up to 11.85 \(\times\) speed boost and 14.86 \(\times\) communication reduction compared to the SoTA work, while it is sufficiently efficient for working on resource-constrained devices.

With the advent of the big data era, the exponen-tially growing data processing requirements pose a huge challenge to data compression. Existing FPGA hardware acceleration schemes have many problems and a new hardware acceleration scheme needs to be explored. There are a large number of parallelizable loops in the data compression algorithm, so they can be accelerated by vectorization. In this paper, we improve RISC- V Vector Extension (RVV) for the data compression. We analyze five common compression algorithms and design a class of vector adjacency instructions for vectorization acceleration for hotspot loops in compression algorithms that cannot use RVV vectorization. We design a decoupled vector arithmetic unit for these instructions that is able to complete computations with data-dependent loops in a non-blocking way. The open source vector processor Ara is used to implement our ideas and is synthesized and implemented on the Alveo U50. The results show that our work brings a maximum speedup of 13.24x in cycle count.

Although Deep Neural Network (DNN) architectures have made some breakthroughs in computer vision tasks, they are not close to biological brain neurons. Spiking Neural Network (SNN) is highly expected to bridge the gap between artificial computing systems and bio-systems. And it also shows great potential in low power computing. This paper presents a low power hardware accelerator for SNN inference using systolic array, and a corresponding software framework for optimization. First, we give the hardware design which adopts systolic array inspired by explorations of SNN. Then we ensure correct data mapping for systolic array for the sake of computational correctness. Next, we use compression methods for decreasing both the runtime and memory footprint. Finally, we make the systolic array size-configurable to adapt to different input, so as to reduce computational overhead. We implement the accelerator on Xilinx FPGA V7 690T. The experimental results show that SNN inference on our scheme suffers little loss on accuracy (less than 0.1%) on MNIST and Fashion-MNIST, and the runtime of the time-consuming layers decreases. The total power of our scheme is 0.745 W at 100 MHz.

In embedded processors, the RAM resources required by branch predictor compared to desktop or server processors are far from being reached. Utilizing the limited resources to design superior performance branch predictor has become urgent challenge. In this paper, we exploit the performance of complex TAGE implemented in ultra-small RAM processor. We first define design space exploration problem of the TAGE under the constraints of given RAM size and maximum global history register length. Then, based on the trace-driven simulation, the improved Particle Swarm Optimization algorithm is used to efficiently explore the specific parameters, rewarding design parameters with high prediction accuracy under RAM ranging from 0.125KB to 4KB. We found that, for the traces of this paper, the parameters under the 1.5KB RAM explored by our algorithm can achieve adequate accuracy. The performance loss is considerably small if we reduce the RAM resources from 8KB to 1.5KB. In addition, the misprediction rate of 1.5KB TAGE are reduced by 63.41% compared to 1.5KB Bi-mode. And, 0.25KB TAGE has almost the same accuracy with 4KB GShare.

Branch predictors are important components that affect the performance of modern microprocessors. Many of the existing prediction simulation platforms either only consider accuracy computed with coarse-grained updating model, or just are the low speed full system simulators. In this paper, We present SimpleBP, a lightweight prediction simulator based on trace driven. It leverages the SystemC language to simulate branch predictor at clock cycle granularity. Also, the CACTI tools is integrated to evaluate area and power consumption. Using SimpleBP, we first make hardware design analysis in a 64Kits storage budget with new added features(feedback delay, fetch width and RAM port number). The experimental results show that the prediction accuracy loss is less than 2% when the feedback delay increased. Under the same RAM area, when fetch width modified, various traces show different accuracy changes. When the area used for dual-port is saved to construct more entries of the subpredictors, the accuracy improvement is about 2.45%. Then, considering these new features, this paper does example optimization exploration of RAM size and subpredictors number through SimpleBP, and the results show many meaningful differences with the results simulated through other simulation platforms.

Besides the accuracy of prediction, chip area occupancy and power consumption also should be taken into account in the design of branch predictors. Many of the previous prediction simulation platforms have either only considered accuracy computed with coarse-grained updating model, or just been the low-speed full system simulators. In this paper, We presents SimpleBP, a lightweight prediction simulator based on trace driven. It leverages the SystemC language to simulate branch predictor at clock cycle granularity. And the CACTI model is introduced to evaluate area and power consumption. The experiment results show that SimpleBP can accurately give multiple evaluations of branch predictors.

Microarchitecture optimization for processor design is a must to achieve target system performance. Provided the register transfer level (RTL) model in real chip design, this paper proposes MOFPGA system, which uses field programmable gate array (FPGA) prototyping as an effective method for fine-grain microarchitecture optimization. It is a fast, reconfigurable, and visible platform with zero impact on the performance of the monitored processor. MOFPGA implements a complete computing platform equipped with a modern out-of-order processor and is able to achieve 60 MHz processor frequency. Besides general FPGA implementation techniques such as multi-port SRAM design and gate-clock conversion, extensive optimization efforts are done to improve the FPGA performance of mapping such a large core. To our knowledge, MOFPGA is the first published FPGA system that implements a modern out-of-order processor running at such high frequency and can report the real SPEC CPU2000 evaluation results.

This paper proposes stream model execution (SME), a new architectural technique that supports the efficient utilization of single-instruction multiple-data (SIMD) engines on general-purpose processors. SME adopts lightweight streaming processing as the intermediate representation. This process uses a hardware–software co-design approach to support efficient SIMD compilation and utilization. From a hardware perspective, the micro-architecture of SIMD engines is enabled for stream support to provide the key components to address the limitations of SIMD utilization, such as data rearrangement and non-consecutive memory access. Thus, sequential code can be compiled efficiently through a two-step procedure (i.e. C code → SME C code → vectorized code) and then executed by the SME hardware. Our experimental evaluation shows that SME can outperform previous optimization techniques by an average of 58% for multimedia kernels and 26% for applications.

Multicore architectures with Network-on-Chips (NoCs) have been widely recognized as the de facto design for the efficient utilization of the continuously increasing density of transistors on a chip. A key challenge in designing such an NoC-based multicore processor is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based protocols, therefore scaling to a large number of cores. However, conventional directory structures add significant indirection delay to cache-to-cache accesses in larger multicore processor. In this article we propose a novel hardware coherence technique, called integrated coherence prediction (ICP). This approach adopts a prediction technique for managing shared data to reduce or eliminate the cache-to-cache delay in coherence accesses. ICP has two unique features that differ from previous coherence prediction techniques. First, ICP introduces a new integrated prediction scheme that combines two kinds of predictors: owner predictor, which predicts the data writers and avoids the indirection through directory, and data predictor, which predicts the access address and prefetches data from remote nodes directly. Second, ICP uses a request replication method to reduce the negative effect of wrong owner prediction operations, thus facilitating overall performance improvement. We present the design and implementation details of the ICP approach. Using detailed full-system simulations, we conclude that the ICP provides a cost-effective solution for designing high-performance multicore processors.

Multicore designs have emerged as the dominant organization for future high-performance microprocessors. Communication in such designs is often enabled by Networks-on-Chip (NoCs). A new trend in such architectures is to fit a Message Passing Interface (MPI) programming model on NoCs to achieve optimal parallel application performance. A key issue in designing MPI over NoCs is communication protocol, which has not been explored in previous research. This article advocates a hardware-supported communication mechanism using a protocol-adaptive approach to adjust to varying NoC configurations (e.g., number of buffers) and workload behavior (e.g., number of messages). We propose the ADaptive Communication Mechanism (ADCM), a hybrid protocol that involves behavior similar to buffered communication when sufficient buffer is available in the receiver to that similar to a synchronous protocol when buffers in the receiver are limited. ADCM adapts dynamically by deciding communication protocol on a per-request basis using a local estimate of recent buffer utilization. ADCM attempts to combine both the advantages of buffered and synchronous communication modes to achieve enhanced throughput and performance. Simulations of various workloads show that the proposed communication mechanism can be effectively used in future NoC designs.

This paper proposes dynamic streamization model execution (DSME), a dynamic vectorization technique for single instruction multiple data (SIMD) engines on multicore architectures. The technique uses stream model as intermediate representation for programs to optimize the combination of computation and memory accesses of SIMD engines in general-purpose (GP) designs. DSME allows the dynamic placement of computations on different cores when they are not in use to utilize multiple SIMD engines. This study also discusses hardware extensions to existing GP processor designs as well as related compiler extensions that use the special hardware components. Our extensive experiments demonstrate that performance gains of DSME can be achieved.

Energy is one of the most crucial issues in Wireless Sensor Networks (WSNs). Hierarchical routing protocols are best known for energy efficiency. In this paper, we propose an energy-efficient multi-hop hierarchical routing protocol which balances the load of network and reduces the cluster heads energy dissipation. According to the density of sensor nodes in monitoring area, the protocol can dynamically determine the size of the cluster. Furthermore, we propose a weight function to dynamically select the next hop appropriately and transmit data by multi-hop manner. Simulation results show that the new protocol can reduce energy consumption and obviously improve the network lifetime.

In this paper, we design a QoS Guaranteed Dynamic Bandwidth Allocation (QGDBA) scheme for a unique OFDMA-PON architecture. In the scheme, we apply statistical method to dynamically allocate bandwidth, iteration algorithm to fully utilize the frames and United-Priority to guarantee QoS of differentiated services. From the simulation results, we find the scheme can provide efficient bandwidth allocation for the next-generation OFDMA-PON.

Buffer resources are key components of the on-chip router, shared-buffer structures are proposed to improve performance and reduce power consumption. This paper presents a novel on-chip network router with a shared-buffer based on Hierarchical Bit-line Buffer (HiBB). HiBB can be configured flexibly according to traffics and its inherent characteristic of low power is also noticeable. Moreover, we propose two schemes to further optimize the router. First, a congestion-aware output-port allocation scheme is used to assign higher priority to packets heading to light-loaded directions, and the congestion situation of the total network will be addressed. Second, an efficient run-time Virtual Channel (VC) regulation scheme is proposed to configure the shared buffer, so that VCs are allocated according to the loads of network. Experimental results show that the proposed HiBB router with about 6.9% area savings outperforms the generic router under different traffic patterns. The power consumption of the HiBB router can also be reduced up to about 70% of the generic router under light traffics, while it may exceed that of the generic one up to about 3.7–5.7% under heavy traffics for the increased flit transmissions.

Strict Priority Queueing (SPQ) andWeighted Round Robin (WRR) are two common scheduling techniques to achieve Quality-of-Service (QoS) while using shared resources. Based on network calculus, we build analytical models for traffic flows under SPQ and WRR scheduling in on-chip wormhole networks. With these models, we can derive per-flow end-to-end delay bound. We compare the service behavior and show that WRR is not only more fair but also more flexible for QoS provision. To exhibit the potential and flexibility enabled by WRR, we develop a weight allocation algorithm to automatically assign proper weights for individual flows to satisfy their delay constraints. In particular, the weights are assigned in a way not more than necessary, in other words, to approach flows' delay constraints in order to leave room for other flows. Our experimental results validate our analysis technique and algorithms.

Software-based code cache systems are the key element in the dynamic translation system or optimization system to store the translated or optimized code for reuse. Translated code is organized in terms of code blocks in the code cache which transfers execution to the next code block through a control transfer instruction. As the target address of the control transfer instruction is in the form of its source program counter, the code cache system has to check the address mapping table for the translated program counter of the target address before entering the required code block. This will cause the performance degradation. As the target address of the direct control transfer instruction is fixed during the execution of a program, its source target address can be replaced with the translated target address. A direct control transfer chaining approach which occupies specific software assists is proposed in this paper. Evaluation of DCTC is conducted on a code cache simulator. The experiment results show the dramatic performance improvement brought by DCTC.

Most of the present optical interconnect networks within the high performance computers require either the buffering and opto-electonic conversion of the data packets or the pre-assigning of the optical path from the source to destination, which to a certain extent influence the performance metrics such as latency and throughput. Aiming at the limitation mentioned above, a hybrid optical-electrical interconnection for high performance computer system named bufferless optical interconnection network (BOIN) is brought forward together with the link control protocol and deadlock/livelock free routing algorithms. The upper bound of the data transmission latency within BOIN is also given. Experimental simulation is based on the comparison of BOIN and the other two similar networks. The results show that BOIN has advantages over the other two that it can deliver high throughput at low latency, which can well satisfy the need for high performance computing systems.

Supporting unbounded transactions and operating system (OS) are two notable challenges that need to be efficiently resolved by practically accepted hardware transaction memory (HTM) systems. Current proposals that heavily rely on traditional cache system to handle version management or conflict detection support poorly to resolve these two challenges. Traditional approach brings either unavoidable design complexity or large performance costs. We propose DTM (decoupled transactional memory), a comprehensive hardware-based solution which follows a new design approach that fully decouples transaction processing from traditional cache system to resolve these two challenges.

It is challenging to design a high performance memory sub-system for heterogeneous multicore processor FT64-3, which features 18 on chip 64-bit float function units. In this paper, we propose a parallel stream memory architecture that can greatly leverage the design idea of exploiting memory level parallelism for higher memory throughput., Experimental results and analysis for kernel algorithms are presented in the paper to show the efficiency and rationale of our design. By employing our parallel stream memory architercture, the performance of FT64-3 with a is 2–3 orders better than FT64-2 when running at the same clock frequency of 500 MHz, and is comparable to Itanium2 running at 1.6GHz but with less hardware cost.

Stream processors, with the stream programming model, have demonstrated significant performance advantages in the domains signal processing, multimedia and graphics applications. In this paper we examine the applicability of a stream processor to 2-D Jacobi iteration which is widely used to solve partial differential equations, an important class of scientific programs. We first map 2-D Jacobi iteration in FORTRAN version to the stream processor in a straightforward way. In a stream processor system, the management of system resources is the programmers' responsibility. We then present several optimizations, which avail the stream program for 2-D Jacobi iteration, called StreamJacobi, of various aspects of the stream processor architecture. Finally, we analyze the performance of StreamJacobi, with different scales, and the presented optimizations. The final stream program StreamJacobi is from 2.31 to 6.42 times faster than the corresponding FORTRAN programs on a Xeon 5100 processor, with the optimizations playing an important role in realizing the performance improvement.

Algorithms of Active Shape Model, as one of the most popular methods for recognizing non-rigid objects, require huge computation power for real time people tracking. After analyzing the parallel characteristics of the algorithm, we propose a deep pipelined structure for accelerating the Active Shape Model algorithm. The computing engine is organized into a deep pipeline network composing of multiple floating-point arithmetic units, including adders, multipliers, dividers and SQRT etc. In the optimization of the memory efficiency for loading random data in large images during the step of local search, we propose an on-chip buffer scheme to eliminate random accesses to off-chip memory. Experimental results show that our FPGA implementation achieves over 15 times of speedup compared with the software implementation in Pentium 4 computer.