As analog and digital circuits have become more intertwined, we need to create a validation approach that handles both circuit types gracefully. This paper proposes a model-first approach, where one creates functional models of the analog blocks that will work in a HDL simulator, and then uses these models in the same way as HDL models are used for other standard cells: they are used in the full system validation, and the underlying implementations are validated to ensure they meet this specification. While creating functional models for the analog blocks might seem difficult, almost all analog blocks can be modeled as linear systems and we use this property to help create the required functional model.

This paper proposes a circuit optimization approach that can ease the computational burden on the simulation-based circuit optimizers by leveraging simple design equations that reflect the designer's intent. The technique is inspired by continuation methods (a.k.a. homotopy) in numerical analysis where a hard problem is solved by constructing an easier problem first and gradually refining its solution to that of the hard problem. In a circuit optimization context, the designer's simplified equations for the circuit serve as the easier problem. These simplified design equations are easy to write as they need not be completely accurate and have intuitive, well-understood solutions. Nonetheless, in several circuit examples, it was found that the designer's equations serve as better guidance than the conventional, fixed-point equations. As a result, the proposed approach demonstrates the better convergence to the desired solution with less computational efforts.

Nanotechnology promises to open up new ways of scaling CMOS circuits by introducing new materials. For example, a hybrid circuit of CMOS gates and carbon nano-tubes (CNT), NEMS relay logic and emerging memory devices have been proposed for future nano-scale Field Programmable Gate Arrays (FPGAs). Hybrid circuits for use as FPGA configurable logic blocks (CLBs) are often proposed in the form of crossbar array architecture. However, many of emerging devices, such as NEMS relays, are not two terminal devices and are thus difficult to be used in the crossbar. On the other hand diode-based logics that are two-terminal devices that can be used in the crossbars, lack signal gain and inversion capability, which makes logic implementation with them difficult. We present nano-magnet/CMOS hybrid circuit using Magnetic Coupled Spin-Torque Devices (MCSTDs) to solve the signal gain and signal level restoration problems, allowing a crossbar array layout to be used throughout the entire crossbar array architecture FPGA. MCSTD consists of two spin torque input devices at the perimeter of a larger output device that serve as biasing dots and manipulate the magnetic reversal energy barrier of the center spintorque device. MCSTDs can implement entire Boolean logic (NAND, NOR, XOR, XNOR and NOT) simply by changing the location of the input spin-torque device and the magnetic shape anisotropy of the center device. The unique features of this logic include: 1) nonvolatility, 2) electronic gain for fan-out and signal restoration and 3) fewer devices to realize most logic functions (i.e. a single MCSTD gate can realize the entire range of Boolean logic gates, while CMOS takes up to 4 (NAND, NOR) or 16 (XOR, XNOR) transistors). The combination of non-volatility and smaller device count leads to reduced circuit area and lower power consumption. Signal gain is achieved by using asymmetric device dimensions between input and output devices. Area and energy consumption calculation of FPGA Look-Up Table (LUT) are performed to demonstrate the merits of the presented Nano-magnetic/CMOS hybrid circuit compared to CMOS. The results show a 94% savings in area at comparable energy consumptions when compared with 32nm CMOS technology node.

This paper describes an efficient method to characterize the impulse sensitivity function (ISF) of a periodic circuit via periodic AC (PAC) analysis. The paper extends the application of ISF from oscillators to other periodic circuits including flip-flops, latches, clocked comparators, and regenerative amplifiers, in order to characterize their important characteristics such as set-up and hold times, regeneration gain, metastability probability, and sampling aperture/bandwidth. Recognizing that the generalized ISF is a subset of a time-varying impulse response, the ISF is efficiently computed based on periodic time-varying system analysis techniques. Compared to the previous ISF characterization method based on transient simulations, a speed-up of ~5times is achieved.