Habituation is a biological behavior allowing non-critical information to be disregarded enabling more processing resources for critical tasks. We have implemented habituation adaptation in VLSI. Our simulations and experimental results illustrate the habituation response.

We describe a neurally inspired processor with on-chip learning. The processor is capable of providing real-time detection of principle features in complex waveforms and system control. Experimental results of pattern recognition and adaptive control using this chip confirm an array of the processing elements can extract important information from the input and produce reduced dimensional representations of the inputs for efficient categorization and control.>

Time is often the dominant information dimension. Applications for time-dependent adaptive systems include sequence generation and predication, image processing, and dynamic control. We have developed a temporal neural system which is composed of an architecture, processing nodes, and training algorithm. The architecture allows arbitrary connectivity between processing nodes including recurrent connections. The processing node includes higher order conjunctive terms, and the training algorithm allows arbitrarily configured topologies to be trained. We demonstrate the temporal neural system by simulating time series generation and a finite state machine.>

The design and test results for two analog adaptive VLSI processing chips are described. These chips use pulse coded signals for communication between processing nodes and analog weights for information storage. The weight modification rule, implemented on chip, uses concepts developed by E. Oja (1982) and later extended by T. Leen et al. (1989) and T. Sanger (1989). Experimental results demonstrate that the network produces linearly separable outputs that correspond to dominant features of the inputs. Such representations allow for efficient additional neural processing. Part of the adaptation rule also includes a small number of fixed inputs and a variable lateral inhibition mechanism. Experimental results from the first chip show the operation of function blocks that make a single processing node. These function blocks include forward transfer function, weight modification, and inhibition. Experimental results from the second chip show the ability of an array of processing elements to extract important features from the input data.

A new local non-Hebbian unsupervised training rule for limited interconnect structures (TRELIS) is derived. The training rule is based on the model of a neuron as a coherent activity detector. The highly parallel and local nature of the training rule allows efficient silicon VLSI implementation. Because of the locality of the training rule and its dependence solely on the excitation source, a network of any desired size is theoretically possible. The statistical correlation of the inputs with a computing node can be used as a feature or a symbol. Another property of this feature is that scaling of the two inputs by the same constant will not change their correlation coefficient or the node output. Simulation of a network of linear computing nodes with TRELIS for the detection of edges in a dynamically blurred image is included

A description is given of the development of a VLSI smart sensor which borrows some mechanisms used by the human eye to generate abstractions of simple line drawings which are invariant with respect to scale and position. Simulation results are presented to show that the representation generated is invariant with respect to the transformations mentioned above. It is shown that such a sensor is capable of real-time performance, yields a considerably higher resolution than conventional schemes, and is similar in some important respects to the human visual system. Two implementation schemes are described, and the extension of the method to gray-scale images is discussed

The embedding of neural networks in real-time systems performing classification and clustering tasks requires that models be implemented in hardware. A flexible, pipelined associative memory capable of operating in real-time is proposed as a hardware substrate for the emulation of neural fixed-radius clustering and binary classification schemes. This paper points out several important considerations in the development of hardware implementations. As a specific example, it is shown how the ART1 paradigm can be functionally emulated by the limited resolution pipelined architecture, in the absence of full parallelism.

This paper describes a procedure for partitioning logic to minimize the number of gate arrays required to implement the logic. The procedure consists of three algorithms to perform initial, iterative, and interactive logic partitioning. Results are presented using three different logic circuits ranging in size from 14 000 gates to 26 000 gates.