The role of ATE is changing from the traditional just go/no go classification to supporting yield learning and adaptive test methodologies as well. This new role demands additional functionalities (e.g. real-time test program control) from the tester as well as puts new requirements on the existing functionalities (e.g. throughput of error capture). This panel will discuss whether the existing ATE architectures are ready for these challenges and what changes need to be made if any to meet the requirements of new role.

The analysis of linked faults (LFs), which are faults that influence the behavior of each other, such that masking can occur, has proven to be a source for new memory tests, characterized by an increased fault coverage. However, many newly reported fault models have not been investigated from the point-of-view of LFs. This paper presents a complete analysis of LFs, based on the concept of fault primitives, such that the whole space of LFs is investigated and accounted for and validated. Some simulated defective circuits, showing linked-fault behavior, will be also presented. The paper establishes detection conditions along with new tests to detect each fault class. The tests are merged into a single test March SL detecting all considered LFs. Preliminary test results, based on Intel advanced caches, show that its fault coverage is high as compared with all other traditional tests and that it detects some unique faults; this makes March SL very attractive industrially.

The analysis of linked faults has proven to be a source for new memory tests, characterized by an increased fault coverage. The paper gives a set of five new tests to target all possible linked faults. The tests are merged into a single test, March SL, detecting all faults in the linked fault space. The preliminary test results of an experiment done at Intel are reported; they show that March SL scores high and detects some unique faults.

This paper improves upon the state of the art in testing word oriented memories. It first presents a complete set of fault models for intra-word coupling faults. Then, it establishes the data background sequence (DBS) for each intra-word coupling fault. These DBSs will be compiled into a (1 + 28 * [log/sub 2/B]) * n/B test with complete fault coverage of the target faults, where n is the size of the memory and B the word size. The test length can be reduced to 29 * n/B when the intra-word faults are restricted to physical adjacent cells within a word.

This paper begins with a brief overview of realistic fault models for multi-port SRAMs with p ports, divided into p classes: single-port faults, two-port faults,..., p-port faults. Except for single-port faults, all other fault classes cannot be detected with the conventional (single-port) memory tests; they require special tests. Next, the paper presents a set of three linear single-addressing tests for unique multi-port memory faults (p > 2) that will be merged into a single test.

The use of deep submicron process technologies presents several new challenges in the area of manufacturing test. While a significant body of work has been devoted to identifying and investigating design challenges in nanometer technologies, the impact on test strategies and methodologies is still not well understood. This paper highlights the challenges to current test methodologies arising from technology driven trends, and will present an overview of emerging techniques that address deep submicron test challenges.

Spurred by technology leading to the availability of millions of gates per chip, system-level integration is evolving as a new paradigm, allowing entire systems to be built on a single chip. Being able to rapidly develop, manufacture, test, debug and verify complex SOCs is crucial for the continued success of the electronics industry. This growth is expected to continue full force at least for the next decade, while making possible the production of multimillion transistor chips. However, to make its production practical and cost effective the industry road maps identify a number of major hurdles to be overcome. The key hurdle is related to test and diagnosis. This embedded tutorial analyzes these hurdles, relates them to the advancements in semiconductor technology and presents potential solutions to address them. These solutions are meant to ensure that test and diagnosis contribute to the overall growth of the SOC industry and do not slow it down. This embedded tutorial in addition presents the state of the art in system-level integration and addresses the strategies and current industrial practices in the test of system-on-chip. It discusses the requirements for test reuse in hierarchical design, such as embedded test strategies for individual cores, test access mechanisms, optimizing test resource partitioning, and embedded test management and integration at the System-on-Chip level. Processor cores being one of the most common cores embedded in a SOC, issues related to self-testing embedded processor cores are addressed. Future research challenges and opportunities are discussed in enabling testing of future SOCs which use deep submicron technologies.

Today's semiconductor manufacturers are moving to more DFT and structurally based testing to reduce capital and engineering investments for test. A number of test methodologies essential for delivering acceptable product quality face new challenges as the industry moves to new process technologies below 200 nm and devices in the GHz range as designs depart from "pure CMOS" with new types of circuits to deliver more performance and lower power. VLSI logic performance has become limited more by interconnect and parasitic reactance than transistor performance and will be more so as devices that push the limits of noise and supply scaling towards 1.O V. The "tails" of defect-device interactions will increasingly include more failures that are sensitive to speed, temperature and voltage, i.e., test coverage completeness is less likely to occur with only stuck at based testing. The industrial test challenge is to keep up with these "tails": to understand how they are reshaped by ongoing changes in circuits and process technologies and to reshape old and add new DFT and test methodologies to enable acceptable product quality at acceptable cost moving forward. Actual examples of "tails" of defect coverage learnings and tradeoffs will be presented as part of this special session at the conference.