This paper presents a new spatio-temporal motion estimation algorithm and its VLSI architecture for video coding based on algorithm and architecture co-design methodology. The algorithm consists of the new strategies of spatio-temporal motion vector prediction, modified one-at-a-time search scheme, and multiple update paths derived from optimization theory. The hardware specification is for high-definition video coding. We applied the ME algorithm to H.264 reference software. Our algorithm surpasses recently published research and achieves close performance to full search. The VLSI implementation proves the low cost feature of our algorithm. The algorithm and architecture co-design concept is highly emphasized in this paper. We provide some quantitative example to show the necessity of algorithm and architecture co-design

This paper presents a new spatio-temporal motion estimation algorithm for video coding. The algorithm is based on optimization theory and consists of the strategies including 3D spatio-temporal motion vector prediction, modified one-at-a-time search scheme, and multiple update paths. The simulation results indicate our algorithm is better than other recently proposed ones under the same computational budget and is very close to full search. The low-cost feature and regular demand of computational resource make our algorithm suitable for VLSI implementation. The algorithm also makes single chip solution for high-definition coding feasible

Motion-adaptive de-interlacing algorithm selects from inter-field and intra-field interpolations according to motion. Correct determination of motion information is essential for this purpose. Fine textures, having high local pixel variation, tend to cause false detection of motion. This paper proposed a texture detection mechanism utilizing multiresolution technique to improve the correctness of detection. A recursive 2-field algorithm is also proposed to reduce the memory cost in 4-field method. This algorithm provides better perceptual visual quality than other motion adaptive de-interlacing as shown by the experimental results.

This paper presents a frame level optimal rate control scheme based on the proposed rate and distortion functions. A linear rate-quantizer model and a linear distortion-quantizer model are proposed to perform rate-distortion optimization. The coefficients of rate distortion models are estimated by linear regression with the past rate distortion characteristics. We propose the two-stage strategy for rate-distortion optimization. First we use Lagrange multiplier optimization approach to obtain the closed-form solution based on our rate distortion models. Then we take the inter-frame dependency into account to further adjust bit rate allocation. We apply our optimal rate control algorithm to H.264, and the proposed algorithm outperforms JVT-G012 rate control scheme in terms of average PSNR.

This paper presents a unified systolic architecture for inter and intra predictions in H.264/AVC decoder. To increase hardware utilization and minimize cost, we combine inter and intra predictions by a reprogrammable FIR filter, which is further implemented using systolic array. For intra prediction, the boundary pixels are reshuffled before feeding into the systolic array. For inter prediction, the 2-D interpolation is conducted through separable 1-D filtering. As compared with the state-of-the-art approaches, our architecture provides higher performance while maintaining relatively lower cost and input bandwidth. Specifically, up to 4x throughput improvement has been achieved. Moreover, the input bandwidth is significantly reduced. Further, combining inter and intra predictions saves the cost by 22~88%.