An efficient automatic test pattern generator for I/sub DDQ/ current testing of CMOS digital circuits is presented. The complete two-line bridging fault set is considered. An adaptive genetic algorithm (GA) is used to generate compact test sets. Experimental results for ISCAS85 and ISCAS89 benchmark circuits are presented. The results show that GA-based test generators are very well suited for generating compact test sets for I/sub DDQ/ testing of bridging faults.

The contribution of this paper on the diagnosis (fault location) of CMOS bridging faults is threefold: First, the traditional fault dictionary (referred to as the full dictionary in this paper) is evaluated at the circuit level using a mixed-mode fault simulator. The fault set consists of randomly-generated gate input/output bridging faults. By using mixed-mode gate- and electrical-level detection methods, good diagnostic capability is achieved using only gate-level generated test sets. Second, we evaluate two reduced fault dictionaries, the pass/fail dictionary and the count dictionary. Finally, the effectiveness of I/sub DDQ/ for diagnosis is examined. The results show that I/sub DDQ/, combined with the proposed voltage detection methods, achieves the highest diagnostic performance, with nearly complete diagnosis.>

The contribution of this paper on the diagnosis (fault location) of CMOS bridging faults is threefold: First, the traditional fault dictionary (referred to as the full dictionary) is evaluated at the circuit level using a mixed-mode fault simulator. The fault set consists of randomly-generated gate input/output bridging faults. By using detection methods good diagnostic capability is achieved using only gate-level generated test sets. Second, the authors evaluate two reduced fault dictionaries, the pass/fail dictionary and the count dictionary. The results show the performance of the much smaller pass/fail dictionary is nearly equal to the full dictionary. Third, the effectiveness of I/sub DDQ/ for diagnosis is examined. The results show that I/sub DDQ/ combined with the proposed voltage detection methods achieves the highest diagnostic performance, with near complete diagnosis.>

Describes an approach for performing transistor-level logical fault simulation of VLSI MOS circuits. The method is based on a recently introduced algebraic approach to switch-level simulation. The faults considered are grouped into four sets: node stuck-at, transistor stuck-open, transistor stuck-on, and bridging faults. The authors consider concurrent fault simulation implementation, and compare, using typical examples, the computational and storage requirements of including all faults in the fault list in one simulation run versus using multiple runs with different fault groupings. Both output voltage and supply current monitoring are used for fault detection.>

The authors describe a method for performing transistor-level logical fault simulation. The method relies on switch-level modeling and uses a switch-level matrix-equation formulation and solution into which fault models are inserted in a straightforward manner. The fault models include transistor stuck-at, node stuck-at, and bridging faults. Both output voltage monitoring and current testing are used for fault detection. The approach has been implemented in a concurrent fault simulator and tested using both combinational and sequential circuit benchmarks. The results of the simulator compare very favourably with existing switch-level fault simulators while allowing more complete transistor-level fault models to be included.>