In hierarchical test generation, the test vectors for the low level structure of the module under test are computed and then justified at a high level. In the module test computation procedure, a low level ATPG tool is conventionally applied to the complete structure of that particular module without adding extra information. Due to the architectural level functional constraints applied to the inputs of that module, many of the test vectors being computed are not justifiable at the high level. Therefore, high efficiency cannot be achieved without managing the functional constraint problem in the hierarchical ATPG process. In this paper, both top-down and bottom-up approaches are addressed. It is shown that the valid control code abstraction and test cube justification techniques are very effective to overcome the architectural level functional constraint problem and to achieve high efficiency in test computation. The proposed algorithms have been implemented in our hierarchical ATPG package and promising experimental results have been derived. We conclude that architectural level functional constraints can be efficiently avoided through these techniques.

The increasing use of hardware description languages (HDL's) in VLSI design and the emergence of high-level test generation programs has led to an interesting problem. There is a need for design for testability (DFT) techniques that can be applied early in the design phase to improve the effectiveness of ATPG programs on hard-to-test circuits. By an early identification of hard-to-test areas of a circuit, testability can be inserted prior to logic synthesis. In this paper, we first present a comparative study of a gate-level test generator and a high-level test generator by benchmarking them on a common suite of circuits. Based on an evaluation of the results, we propose techniques to automatically extract information from the high-level circuit description that could improve the performance of both ATPG tools. An automatic DFT tool that utilizes VHDL descriptions of the circuit to make an intelligent selection of flip-flops for partial scan is then described. Results on six hard-to-test circuits show that very high fault coverages can be obtained by both a gate-level and a high-level test generator on these circuits after scan. With this detailed study we demonstrate that a DFT tool can make a more efficient and effective selection of partial scan flip-flops by exploiting the high-level circuit information. It can accurately predict the hard-to-test areas of a circuit. Significant improvements in fault coverage and ATPG efficiency, and speedups in ATPG time, can be obtained by a gate-level and a high-level test generator after high-level scan selection.>

Hierarchically designed microprocessor-like VLSI circuits have complex data paths and embedded control machines to execute instructions. When a test pattern has to be applied to the input of an embedded module, determination of a sequence of instructions, which will apply this pattern and propagate the fault effects, is extremely difficult. After the instruction sequence is derived, to assign values at all interior lines without conflicts is also very difficult. In this paper, we propose a separation of test generation process into two phases: path analysis and value analysis. In the phase of path analysis, a new methodology for automatic assembly of a sequence of instructions is proposed to satisfy the internal test goals. In the phase of value analysis, an equation-solving algorithm is used to compute an exact value solution for all interior lines. This new ATPG methodology containing techniques for both path and value analysis forms a complete solution for a variety of microprocessor-like circuits. This new approach has been implemented and experimented on six high-level circuits. The results show that our approach is very effective in achieving complete automation for high-level test generation.>

When a logic module is embedded in a large circuit, the architectural level functional constraints usually cause don't cares at the interface of this module. If the logic of the module is not synthesized using these don't cares, then redundancy may exist making the circuit very hard to test. In this paper, architectural level circuit structural and instruction behavioral information is exploited to analyze functional constraints and extract don't cares. The don't cares are used to optimize the logic of the module and to remove many redundant faults.>

When VLSI circuits such as microprocessors are designed hierarchically, testability issues have to be considered simultaneously with functional specifications to reduce the testing complexity early in the design phase. Accurate testability measures are required to indicate the hard-to-test areas and can be used as a guidance for ATPG. This paper presents a new testability analysis technique operating at a high level using both circuit structural information and assembly-level instruction behavioral information. This testability analysis targets at the popular functional test generation and a modern high level ATPG methodology published in recent literature. The experimental results of testability measures as well as high level ATPG are presented to verify the effectiveness.>

A comparative study of a gate-level test generator and a high-level test generator by benchmarking them on a common suite of circuits is presented. Based on the examination of the results DFT techniques that use high-level circuit information are proposed. The results obtained after partial scan selection by a high-level DFT tool are compared with results obtained by a gate-level partial scan tool. This detailed comparative study demonstrates that a DFT tool can make a more effective selection of partial scan flip-flops by exploiting the high-level circuit information, and by accurately predicting the hard-to-test areas of a circuit.>

This paper presents techniques to utilize high-level structural, functional and register-transjer information to perform design-for-testability (DFT}. An automatic tool which utilizes VHDL descriptions of the datapath and control unit of sequential circuits to make an intelligent selection of scan pip-pops is described. This DFT tool ADEPT can make design enhancements early in the design phase. Results on four hard-to-test circuits show that very high fault coverages can be achieved by both a gate-level and a high-level test generator on these circuits after scan selection. Fewer scan jlip-flops were chosen as compared to a gate-level partial scan selection.

Hierarchically designed microprocessor-like VLSI circuits have complex data paths and complex embedded control machines to execute instructions. When a test pattern has to be applied to the input of an embedded module, determination of a sequence of instructions, which will apply this pattern and propagate the fault effects, is extremely diflcult. In this paper, we present a new methodology for automatic assembly of a sequence of instructions to satisfy the internal test goals. Combined with the previous equation-solving approach, this new high level ATPG methodology forms a complete solution for a variety of microprocessor-like circuits. This new approach has been implemented and experimented on three high level circuits. The results show that our approach is very effective in achieving complete automation for high level test generation.

A novel architectural level test generation methodology is proposed to solve both data flow path conflicts and data flow value conflicts. For each pattern to be justified at a high level, an instruction sequence and the underdetermined system of nonlinear equations are derived based on preprocessing information. The solution of the system of equations is calculated by a signal-driven discrete relaxation algorithm without making any high-level decisions. The test generation is performed by recursively assembling the instruction sequence and solving the system of equations. This test generation approach has been implemented, and the tests of several microprocessors have been generated successfully. The results show that this approach is effective and promising.>

In this paper, an ATF’G methodology working at an architectural level is proposed. For the data path portion, the hierarchy of the design is exploited and the dependence on the gate level information is relieved. For the conb’oi faults, gate level algorithms are incorporated with high level approaches to excite the fault and differentiate the fault effect to primary outputs. Due to the fault collapsing effect arid the fault differentiation process, several data types have been defined for the manipulation alf all possible fault e€fects. A functional equivalent model is used for sequential modules, which makes this technique extendable beyond the register-transfer level. The backtracking mechanism used in the control unit has been carefully modified to ensure a complete finite space searching. Some experimerrtal results are presented to show the effectiveness of this approach.