A CMOS charge pump adopting dual charge transfer switches and a transfer blocking technique is presented. Using these techniques, the proposed charge pump eliminates reversion loss and improves driving capability. A test chip is designed in a 46-nm CMOS process, whose evaluation results show that, with no loading current, the proposed CMOS charge pump achieves 9.1% improvement of voltage conversion ratio. They also show that the proposed charge pump provides up to 132% improvement on current driving capability, as compared with the conventional CMOS charge pumps.

A new two-line based inversion driving method is introduced for low-power consumption of display driver ICs. Eliminating the correlation between the chopper stabilization and the polarity of LCD, we can reduce power consumption without noticeable degradation of display quality. Applying the proposed scheme to 17" LCD applications, we achieved 12% power saving in DDI with white patterns and 27% with black patterns.

A power-efficient voltage-mode transmitter for battery powered mobile applications was designed. The proposed transmitter consists of a power optimized 16:2 serializer, a data-aligner, 2:1 multiplexing pre-driver, and an I/O driver with segment control for impedance matching. With scalable low-voltage signaling (SLVS) with the output swing of 200mVp-p and power optimization for digital blocks, 0.37mW/Gb/s power consumption was achieved. The test chip for 4.8 Gb/s interfaces was designed in a 65nm 1.2V supply CMOS logic process. The proposed I/O specifications are appropriate for MIPI M-PHY systems.

In this paper, a low-power embedded pseudo-SRAM adopting novel auto-adjusted self-refresh control scheme has been designed. The proposed self-refresh control scheme automatically extends the self-refresh period by monitoring the number of failed cells using error correction code (ECC). The scheme can provide a substantial reduction of data-retention power consumption by choosing an optimal self-refresh period regardless of process, voltage, and temperature (PVT) variations. A 4-Mb embedded pseudo-SRAM designed in a 45-nm embedded DRAM technology providing 1.1-V 166-MHz random cycle operation achieves 57-uW data retention power consumption at room temperature.

In this paper, presetting pulse-based flip-flop (PSPFF) is proposed. The flip-flop briefly presets its storage nodes to a medium voltage level between VDD and VSS just before input capturing. This presetting operation allows the proposed flip- flop to be faster and more clock-skew tolerant than conventional pulse-based flip-flops. Comparison results using a 80-nm CMOS process technology indicate that PSPFF has 22% improvement on clock-skew tolerance, 20% decrease of data-to-output delay, 22% reduction of power-delay product, and 21% reduction of layout area, as compared to PCSPFF.

This paper presents novel low-cost CMOS temperature sensor for controlling the self-refresh period of a mobile DRAM. In the proposed temperature sensor, the temperature dependency of poly resistance is used to generate a temperature-dependent bias current, and a ring oscillator driven by this bias current is employed to obtain the digital code pertaining to on-chip temperature. This method is highly area-efficient, simple and easy for IC implementation as compared to traditional temperature sensors based on bandgap reference. The proposed CMOS temperature sensor was fabricated with an 80nm 3-metal DRAM process, which occupies extremely small silicon area of only about 0.016 mm2with under 1uW power consumption for providing 0.7°c effective resolution at 1 sample/sec processing rate. This result indicates that as much as 73% area reduction was obtained with improved resolution as compared to the conventional temperature sensor in mobile DRAM.

This paper proposes PVT-invariant single-to-differential signal converter (SDQ applicable to the output circuitry of high-speed DDR SDRAM. The proposed SDC generates PVT-invariant differential-output sampling clock using a phase interpolation technique and a symmetric structure, and improves the aperture window of output data in source synchronous DDR SDRAM. The proposed SDC was simulated using 1.8-V 80-nm DRAM technology. The comparison result indicates that the differential clocks generated by the proposed SDC achieve 80.6% reduction of skew, 76.6% reduction of duty-cycle distortion, 61.7% of reduction of delay variation, and 8.5% reduction of maximum current for a given process, voltage, and temperature (PVT) variations, as compared to conventional SDCs. The I/O interface of a source-synchronous DDR SDRAM designed using the proposed SDC, which is operating at 1.0-Gbps/pin data rate has aperture window increased by 15.3% and ISI improved by 67.7% in comparison to conventional I/O interface.

This paper presents Needle Auto Calibration (NAC) probing technique to measure the electrical characteristics of Probecard for wafer-level test. Probecard needle alignment and probing tasks, which are generally known to be hard and time-consuming, can be done easily through automatic Probecard aligning function of NAC. The inaccuracy problem during measurements by NAC probing due to difficulties of calibration is compensated by adapter characterization and de-embedding techniques. According to our experimental results, the inaccuracies of group delay, insertion loss and phase characteristic are decreased from 30.4% to 2.71%, from 1.75% to 0.53%, and from 35.2% to 1.32%, respectively.

In this paper, a novel CMOS differential logic family, called data-dependent evaluating latched CMOS logic (DELL), is proposed for use in low-power VLSI. The proposed logic family discharges internal precharge nodes on demand, and thus, statistically reduces the power consumption during logic operation. The self-resetting version of the logic family can also boost the operating clock frequency by performing precharge operation as early as possible. It has the additional advantage of clock power reduction by reducing the clock load. The proposed logic family was designed using 0.35 /spl mu/m CMOS process technology. The comparison results show that the proposed logic family consumes less power than the conventional logic family for the switching activity smaller than 0.7, and achieves a power saving of up to 75%. The improvement of power, delay product is also about 34%.

A novel gate-level high-speed VLSI logic simulation technique with assignable delay is presented that uses bitwise logic operations together with the segmented waveform relaxation method (SWRM). The implementation of the technique on parallel computers is described. Although the proposed technique is similar to the compiled-code method, it does not generate a compiled-code and can handle different delay methods which cannot be handled by the conventional compiled-code method. By using waveform relaxation techniques, the simulation can always find the correct logic level in tightly coupled feedback circuits (such as flip-flops), while event-driven simulation may not give the correct logic levels in these cases. The proposed simulator reduces the memory requirements and computation time by using segmented waveform relaxation. On a single processor the simulator is about one order of magnitude faster than the traditional event-driven simulators and can easily handle tens of thousands of gates.>

A delay model for multiple delay simulation for NMOS and CMOS logic circuits is proposed. For the simple inverter the rise or fall delay time is approximated by a product of polynomials of the input waveform slope, the output loading capacitance, and the device configuration ratio, with the polynomial coefficients determined so as to best fit the SPICE simulation results for a given fabrication process. This approach can easily be extended to the case of multiple-input transitions. The simulation results show that the proposed modes can predict the delay times within 5% error and with a speedup of three orders of magnitude for several circuits tested as compared with the SPICE simulation.>