Modern multimedia, gaming and entertainment devices epitomize high-growth, consumer-driven applications for silicon. 2006 has been a year that launched several high-profile gaming systems, and major changes in home networking. This year has also witnessed the emergence of the digital home and the ePC, as well as continued struggles for control of the home gateway. Mobile-digital has continued with the fusion of media, telephony, and digital-mobile TV. The industry's ability to rapidly evolve such consumer-centric systems brings to bear all of the technology competencies required for cutting-edge IC designs, as well as for tools and methodologies that support those designs. Multimedia and gaming chips are pushing the leading edge of EDA technology forward on fronts that include architectural synthesis, high-speed clocking, power management, verification, and IP reuse. As just one example, GPU operations per second are growing significantly faster than desktop CPU operations per second, while at the same time, GPU design teams often place less, emphasis than microprocessor teams on circuits and layout, and more emphasis on architecture and design enablement. The confluence of these trends leads to design and CAD solutions that are unique in the market space. In this panel session, the panelists have been selected to represent five key constituencies: the digital home (Intel), mobile digital TV (Samsung), graphics engines (NVIDIA), advanced displays (Pixelworks), and gaming/multimedia processing (IBM). The panel will address such questions as; what are the underlying chip architectures and roadmaps for key multimedia/entertainment platforms?; what are the key design and technology challenges (or brick walls) for next-generation products, and how will these challenges be addressed?; where will we see the next convergence in devices and platforms?; what other challenges arise from complex supplier and competitor relationships, standards, and other aspects of a globalized market? Other design challenges to be discussed include design enablement (compilers, programming models, etc.), design for IP reuse (configurability, derivatives), and IP management in a world of increasing co-opetition.

Moore's law delivers higher performance and lower cost for FPGAs and ASICs alike, but at the 90nm process node and below, design schedules using the traditional cell-based ASIC design methodology hit a wall of uncertainty. At 90nm and below an emerging alternative ASIC design platform is either Platform ASIC or FPGAs. Which way will the cell-based ASIC designer turn for their next design?Over time, FPGAs and structured/platform ASICs are together poised to replace today's cell-based ASIC market, but which is the real answer to future digital design? Can companies really use these platforms to achieve the system cost reduction and functionality that they need to stay competitive? Which applications will migrate to these platforms the fastest? Is it possible to just tweak the existing cell-based methodology to more efficiently reach the benefits of 90nm process nodes and below? This lively panel will discuss whether it is FPGAs, structured/platform ASICs, or something else that stand to gain the most ground from the projected $25B ASIC market, and why.