The rapid evolution of technology and increasing demand for area-efficient RF-speed communication systems are pushing towards using the CMOS comparators to optimize speed with low power consumption. Ultra-scaled nodes hold significant potential in this context but require complex design-technology co-optimization. In this paper, we focus on the design of such a comparator with load buffer considered using IMEC’s sub-3nm calibrated PDK model. Post-layout simulation results show that the comparator operates at 32 GHz clock frequency, consuming 11.9 fJ energy per operation with 20 mVpp-diffinput from a 1-V supply, for a core area of 1.44 μm2.

This article presents the design methodology and the measurements of a DC-coupled wideband Active Balun fabricated in a 40-nm CMOS process. An auxiliary balun-based phase and amplitude imbalance compensation method is analyzed and implemented, providing broadband imbalance reduction. Differential T-coil peaking is utilized in each balun for bandwidth extension, and a resistive-feedback inverter is used to interface with$50~\Omega $at the input. The designed Active Balun achieves 8.2 dB single-ended to differential gain with 28 GHz 3-dB bandwidth, with a peak phase and amplitude imbalance of 4 degrees and 0.3 dB within the bandwidth, respectively. The measured noise figure remains around 5 dB between 5-20 GHz.

In this paper, an analysis method is presented to mathematically characterize the harmonic current generated by the voltage at fundamental or harmonic frequency in the transistor of a high-frequency harmonic oscillator. Using this analysis method, the relationship between the second harmonic voltages and the fourth harmonic drain current in the transistor is investigated, and the requirement on the second harmonic voltages for fourth harmonic boosting is found. Moreover, an approach of modeling the voltage-current relationship in the transistor of a high-frequency harmonic oscillator at harmonic frequency as an equivalent linear relationship is proposed. This modeling method facilitates the design of the second harmonic embedding network around the transistor, thus helping to propose a harmonic oscillator topology in which the requirement on the second harmonic voltages for fourth harmonic boosting is fulfilled. Using the proposed fourth harmonic boosting technique, a 0.6-THz radiator array is designed in 40-nm bulk CMOS. In measurement, the 0.68-$\text {mm}^{2}$radiator array achieves a radiated power of 0 dBm and a DC-to-THz efficiency of 0.08% at 586.7 GHz under a 0.9-V supply voltage.

This paper proposes a new approach to above-$f_{max}$power detection, using harmonic injection locking of a cross-coupled oscillator and the resulting change in oscillation amplitude. The paper starts with the development of a theoretical framework for this receiver. Two previous methodologies are combined: analyzing an injection-locked oscillator as an active device in a positive feedback loop with a frequency selective network; and the more recently proposed way of modeling non-linearities by using inter-harmonic translation coefficients. Using this framework, a compact equation for the expected voltage response of the receiver is derived. Finally, the design of a receiver consisting of a 200 GHz cross-coupled oscillator with a 600 GHz folded dipole antenna as its tank inductor is discussed. A Noise Equivalent Power (NEP) of 2.3 pW/$\sqrt {\text {Hz}}$is achieved with the proposed receiver.

This paper proposes a technique to enhance the maximum achievable power gain ( GMAX) of the two-port active network (2PAN) in the near- fMAXregion. This technique is based on using the optimized passive-linear-lossy-reciprocal (PLLR) embedding to increase the unilateral power gain ( U) of the 2PAN and accordingly the GMAX. Due to the possibility to increase U, it shows the potential to improve the conventional gain-boosting approach which relies on the passive-linear-lossless-reciprocal (PLLLR) embedding and keeps the U constant. The concept itself is demonstrated on pseudo-differential NMOS pair using lossy capacitive feedback as the PLLR. This structure can serve as a basis for further gain optimization by implementing additional PLLLR embedding on top of it. Finally, by using the mentioned technique, a 190GHz amplifier is implemented in 28nm bulk CMOS technology, achieving 14.3dB of gain with 1.5dBm of PSATand 2.6% of maximum PAE.

This paper proposes a novel integrated oscillator topology based on a transmission line. The frequency is extracted from the delay of the transmission line, which is intrinsically independent of temperature and supply variations. The architecture for the oscillator, guidelines for the design of the transmission line as well as the different building blocks are presented. The architecture is based on a phase-locked loop topology. The transmission line used has a 509 ps delay, an area of 2.26 mm2and a 4.38 dB power loss. The effect of process variations on the transmission line is extensively investigated. A digital driver using CMOS inverters and an analog driver based on an OTA are proposed. Both have a good stability over temperature. The Gilbert cell is proposed as a detector at the output of the transmission line and the corresponding design considerations are shown. Closed loop simulations show fast locking, a variation of 8.3°C between -10°C and 85°C and a variation of 3.70/00for Vdd± 10%.

The design and optimization (both sizing and layout) of mm-wave integrated circuits (ICs) have attracted much attention due to the growing demand in industry. However, available manual design and synthesis methods suffer from a high dependence on design experience, being inefficient or not general enough. To address this problem, a new method, called general mm-wave IC synthesis based on Gaussian process model assisted differential evolution (GASPAD), is proposed in this paper. A medium-scale computationally expensive constrained optimization problem must be solved for the targeted mm-wave IC design problem. Besides the basic techniques of using a global optimization algorithm to obtain highly optimized design solutions and using surrogate models to obtain a high efficiency, a surrogate model-aware search mechanism (SMAS) for tackling the several tens of design variables (medium scale) and a method to appropriately integrate constraint handling techniques into SMAS for tackling the multiple (high-) performance specifications are proposed. Experiments on two 60 GHz power amplifiers in a 65 nm CMOS technology and two mathematical benchmark problems are carried out. Comparisons with the state-of-art provide evidence of the important advantages of GASPAD in terms of solution quality and efficiency.

Existing radio frequency (RF) integrated circuit (IC) design automation methods focus on the synthesis of circuits at a few GHz, typically less than 10 GHz. That framework is difficult to apply to RF IC synthesis at mm-wave frequencies (e.g., 60-100 GHz). In this paper, a new method, called efficient machine learning-based differential evolution, is presented for mm-wave frequency linear RF amplifier synthesis. By using electromagnetic (EM) simulations to evaluate the key passive components, the evaluation of circuit performances is accurate and solves the limitations of parasitic-included equivalent circuit models and predefined layout templates used in the existing synthesis framework. A decomposition method separates the design variables that require expensive EM simulations and the variables that only need cheap circuit simulations. Hence, a low- dimensional expensive optimization problem is generated. By the newly proposed core algorithm integrating adaptive population generation, naive Bayes classification, Gaussian process and differential evolution, the generated low-dimensional expensive optimization problem can be solved efficiently (by the online surrogate model), and global search (by evolutionary computation) can be achieved. A 100 GHz three-stage differential amplifier is synthesized in a 90 nm CMOS technology. The power gain reaches 10 dB with more than 20 GHz bandwidth. The synthesis costs only 25 h, having a comparable result and a nine times speed enhancement compared with directly using the EM simulator and global optimization algorithms.

Design and optimization of microwave passive components is one of the most critical problems for RF IC designers. However, the state-of-the-art methods either have good efficiency but highly depend on the accuracy of the equivalent circuit models, which may fail the synthesis when the frequency is high; or fully depend on electromagnetic (EM) simulations, whose solution quality is high but are too expensive. To address the problem, a new method, called Gaussian Process-Based Differential Evolution for Constrained Optimization (GPDECO) is proposed. In particular, GPDECO performs global optimization of the microwave structure using EM simulations, and a Gaussian process (GP) based surrogate model is constructed ON-LINE at the same time to predict the results of expensive EM simulations. GPDECO is tested by two 60GHz transformers and comparisons with the state-of-the-art methods are performed. The results show that GPDECO can generate high performance RF passive components that cannot be generated by the available efficient methods. Compared with available methods with the best solution quality, GPDECO can achieve comparable results but only costs 20%-25% of the computational effort. Using parallel computation in an 8-core CPU, the synthesis can be finished in less than 0.5 hour.

State-of-the-art synthesis methods for microwave passive components suffer from the following drawbacks. They either have good efficiency but highly depend on the accuracy of the equivalent circuit models, which may fail the synthesis when the frequency is high, or they fully depend on electromagnetic (EM) simulations, with a high solution quality but are too time consuming. To address the problem of combining high solution quality and good efficiency, a new method, called memetic machine learning-based differential evolution (MMLDE), is presented. The key idea of MMLDE is the proposed online surrogate model-based memetic evolutionary optimization mechanism, whose training data are generated adaptively in the optimization process. In particular, by using the differential evolution algorithm as the optimization kernel and EM simulation as the performance evaluation method, high-quality solutions can be obtained. By using Gaussian process and artificial neural network in the proposed search mechanism, surrogate models are constructed online to predict the performances, saving a lot of expensive EM simulations. Compared with available methods with the best solution quality, MMLDE can obtain comparable results, and has approximately a tenfold improvement in computational efficiency, which makes the computational time for optimized component synthesis acceptable. Moreover, unlike many available methods, MMLDE does not need any equivalent circuit models or any coarse-mesh EM models. Experiments of 60 GHz syntheses and comparisons with the state-of-art methods provide evidence of the important advantages of MMLDE.

RF-powered wireless sensor networks demand for ultra-low-energy A/D converters. Such systems have specific requirements, like fast start-up time and supply voltage independence. The presented A/D converter is based on a digital phase locked loop. Two closely matched ring oscillators perform the analog to frequency conversion. The digital output is generated by an in-loop digital proportional-integral filter. The acquisition of the PLL is splitted into coarse and fine tuning to reduce the locking time to less than 30μs. A UMC130 CMOS technology is used to simulate a temperature sensor interface. The energy consumption is maximally 212 pJ per conversion and the effective number of bits is 7 bit in a 0.5 V-1.4 V supply voltage range.

Class E amplifiers are imposed by time-domain constraints. This makes the design of such amplifiers more difficult than other types of amplifiers. This paper presents a new method to analyze class E power amplifiers using state-space equations. A description by these equations makes it possible to find the correct initial conditions that leads to the steady-state solution of the amplifier. Furthermore, it is possible to derive the power balance of the power amplifier based on its state-space equations. The presented method has shown to be very valuable when designing switched power amplifiers. Furthermore, the method can also be applied for power amplifiers that do not fulfill the class E switching conditions.