To reduce defect parts per million (DPPM) on IC products, IDDQ testing can be exploited for identifying the outliers which are potentially defective but not detected by sign-off functional and parametric tests. Conventional IDDQ testing paradigms depending on a simple statistical$6\sigma $rule or engineers’ experience are usually too conservative to effectively identify nontrivial outliers, especially, when spatial correlations are of great concern/influence. In article, an improved convolutional neural network (CNN)-based method can be proposed for IDDQ outlier identification. In the proposed method, the mean and the standard deviation on the IDDQ value inside a die under test (DUT) can be predicted by employing a stochastic regression model. According to the predicted mean and standard deviation, we derive an expected IDDQ interval and identify the DUT as an outlier if its actual measured IDDQ value is beyond the expected interval. From the observation of the experimental results, the improved data preprocessing and the improved CNN-based stochastic regression can be contained to enhance the prediction accuracy of the expected IDDQ intervals. In the improved method, the spatial correlations of the neighboring dice inside a window can be considered by training a CNN-based stochastic regression model with a large volume of industrial data on 28 and 65 nm products. The trained model is highly accurate prediction in the$R^{2}$(0.973) and RMSE (0.626 mA) of the expected IDDQ values on 28 nm product and the$R^{2}$(0.942) and RMSE (2.155 uA) of the expected IDDQ values on 65 nm product. Furthermore, the experimental results show that the trained model can capture the potential defective dice by identifying efficient IDDQ outliers.

Conventional fault models define their faulty behavior at the IO ports of standard cells with simple rules of fault activation and fault propagation. However, there still exist some defects inside a cell (intra-cell) that cannot be effectively detected by the test patterns of conventional fault models and hence become a source of DPPM. In order to further increase the defect coverage, many research works have been conducted to study the fault models resulting from different types of intra-cell defects, by SPICE-simulating each targeted defect with its equivalent circuit-level defect model. In this paper, we propose to improve cell-aware (CA) test methodology by concentrating on intracell bridging faults due to short defects inside standard cells. The faults extracted are based on examining the actual physical proximity of polygons in the layout of a cell, and are thus more realistic and reasonable than those (faults) determined by RC extraction. Experimental results on a set of industrial designs show that the proposed methodology can indeed improve the test quality of intra-cell bridging faults. On average, 0.36 % and 0.47% increases in fault coverage can be obtained for 1-time-frame and 2-time-frame CA tests, respectively. In addition to short defects between two metal polygons, short defects among three metal polygons are also considered in our methodology for another 9.33 % improvement in fault coverage.

In order to reduce defect parts per million, cell-aware (CA) methodology was proposed to cover various types of intracell defects. In this article, we present a novel methodology for generating 2-time-frame (2tf) CA tests based on timing slack analysis. The proposed 2tf CA fault model, aware of timing slack and named TS, defines a fault: 1) on a cell instance basis and 2) based on per-instance timing criticality (according to timing slack). By comparing the derived extra delay against the timing slack of the cell instance, a delay fault can be defined, and according to its severity, the fault can be further classified into small-delay fault or gross-delay fault. In contrast to prior 2tf CA methodology that is on a cell (rather than cell instance) basis and unaware of timing criticality/slack, our methodology can identify “more realistic” faults which really need to be considered, and potentially the cost/effort for testing those 2tf CA faults can be reduced. We also propose a test quality metric, timing slack defect coverage (TSDC), to measure the effectiveness of automatic test pattern generation (ATPG) tests in terms of the ability to detect small-delay TS defects along long paths. Experimental results on a set of 22-nm industrial designs demonstrate that, due to more realistic fault identification, the number of identified small-delay faults can be reduced by 56.8%. With the slack-based ATPG for testing small-delay faults along long paths, TS can reduce the number of test patterns by 33.1% while achieving 0.49% higher TSDC, compared with the results of prior 2tf CA methodology.

GDBN (good die in bad neighborhood) methodology has been regarded as an effective technique for reducing DPPM (defect parts per million), by identifying and rejecting suspicious dice even though they test good. Instead of examining eight immediate neighbors or exploiting simple linear regression, in this paper we propose to employ a window of larger size for broad-sighted recognition of neighborhood, and make best use of the larger window for accurate prediction of the suspicious level for any given die. The proposed methodology is realized by using an artificial neural network (NN), and is a breakthrough of NN-based work for solving the problem of GDBN. Various experiments on two sets of data clearly reveal the superiority of our NN-based methodology over other existing methods. Besides reducing DPPM, our methodology is able to achieve 1. 5X-2X better reduction in the cost for return merchandise authorization (RMA).

In order to reduce DPPM (defect parts per million), IDDQ testing methodology can be exploited for identifying "outliers" which are potentially defective but not detected by signoff functional and parametric tests. Conventional IDDQ testing paradigms depending on a simple statistical 6σ rule or engineers’ experience are usually too conservative to effectively identify non-trivial outliers, especially when spatial correlations are of great concern/influence. In this paper, by employing a stochastic regression model, the mean as well as the variance of the IDDQ of a die under test (DUT) can be predicted. According to the predicted mean and variance, we derive an expected IDDQ range and identify the DUT as an outlier if its actual IDDQ measurement is beyond the expected range. The proposed stochastic regression model is obtained by training a convolutional neural network (CNN) and, based on its primitive property of convolutional kernel mapping with large volume of industrial data, spatial correlations (due to spatially-correlated process variations, etc) can be considered/captured. The trained data-driven CNN is highly accurate in terms of R-square (0.958) and RMSE (0.783), and the percentage of identified outliers (0.047%) is very close to the theoretical reference (0.050%), which validates the efficacy of our proposed methodology.

In order to reduce DPPM (defect parts per million), cell-aware (CA) methodology was proposed to cover various types of intra-cell defects. The resulting CA faults can be a 1-time-frame (1tf) or 2-time-frame (2tf) fault, and 2tf CA tests were experimentally verified to be capable of catching a significant number of defective parts not covered by other conventional tests. In this paper, we present a novel methodology for generating 2tf CA tests based on timing slack analysis. The proposed 2tf CA fault model, aware of timing slack and named TS, defines a fault (i) on a cell instance basis, and (ii) based on per-instance timing criticality (according to timing slack). More explicitly, for each cell instance with a specific defect injected, we check its output capacitive load and derive the corresponding extra delay. By comparing the extra delay against timing slack of the cell instance, a delay fault can be defined, and according to its severity, the fault can be further classified into small-delay fault or gross-delay fault. In contrast to prior 2tf CA methodology that is on a cell (rather than cell instance) basis and unaware of timing criticality/slack, our methodology can identify “more realistic” faults which really need to be considered, and potentially the cost/effort for testing those 2tf CA faults can be reduced. Experimental results on a set of 28nm industrial designs demonstrate that, due to more realistic fault identification, the numbers of identified small-delay faults and corresponding test patterns to be applied can be reduced by 35.1% and 24.1% respectively, leading to 40.7% reduction in the runtime of ATPG.

Conventional fault models define their faulty behavior at the IO ports of standard cells with simple rules of fault activation and fault propagation. However, there still exist some defects inside a cell (intra-cell) or between two cells (dual-cell) that cannot be effectively detected by the test patterns of conventional fault models and hence become a source of DPPM. In order to further increase the defect coverage, many research works have been conducted to study the fault models resulting from different types of intra-cell and dual-cell defects, by SPICE-simulating each targeted defect with its equivalent circuit-level defect model. However, it was considered computationally infeasible to simulate every possible defective scenario for a cell library and obtain a complete set of cell-level fault models. In this paper, we present a new dual-cell-aware (DCA) framework based on examining the layout of two adjacent cells (i.e., a dual cell) to identify potential defects, where time-consuming RC extraction can be avoided and the runtime for SPICE simulation can be reduced. Experimental results and silicon data on a SoC product show that the proposed DCA framework can not only save runtime significantly but also maintain the promising efficacy of DCA tests for the objective of lowering DPPM.

To measure the variation of device Vtrequires long test for conventional wafer acceptance test (WAT) test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of Vtfor a large number of designs under test (DUTs). The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of Vtbased only on the combined Idmeasured from parallel connected DUTs. The proposed framework can further minimize the total number of Idmeasurement required for prediction models while limiting their accuracy loss. The experimental results based on the SPICE simulation of a UMC 28-nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R-squared for predicting either Vtmean or Vtvariance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve a 120.3 × speedup on overall test time for test structures with 800 DUTs.

This paper presents a statistical model-fitting framework to efficiently decompose the impact of device Vt variation and power-network IR drop from the measured ring-oscillator frequencies without adding any extra circuitry to the original ring oscillators. The framework applies Gaussian process regression as its core model-fitting technique and stepwise regression as a pre-process to select significant predictor features. The experiments conducted based on the SPICE simulation of an industrial 28nm technology demonstrate that our framework can simultaneously predict the NMOS Vt, PMOS Vt and static IR drop of the ring oscillators based on their frequencies measured at different external supply voltages. The final resulting R squares of the predicted features are all more than 99.93%.

This paper introduces a novel fault model, called the dual-cell-aware (DCA) fault model, which targets the short defects locating between two adjacent standard cells placed in the layout. A layout-based methodology is also presented to automatically extract valid DCA faults from targeted designs and cell libraries. The identified DCA faults are outputted in a format that can be applied to a commercial ATPG tool for test generation. The result of ATPG and fault simulation based on industrial designs have demonstrated that the DCA faults cannot be fully covered by the tests of conventional fault models including stuck-at, transition, bridge and cell-aware faults and hence require their own designated tests to detect.

To measure the variation of device Vtrequires long test for conventional WAT test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of Vtfor a large number of DUTs. The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of Vtbased on only the combined Idmeasured from parallel connected DUTs. The experimental results based on the SPICE simulation of a UMC 28nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R-squared for predicting both of Vtmean and variance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve 42.9X speedup in turn of the required iterations of Idmeasurement per DUT.

This paper presents a novel diagnosis technique for multiple defects. This technique proposes a simple heuristic to partition the failures log so that hard-to-detect defects and easy-to-detect defects are likely to be separated. This technique requires only commercial diagnosis software with a simple add-on tool. No customized diagnosis software is needed. Simulations on benchmark circuits demonstrated the effectiveness of the proposed technique. Real silicon experiments on a real industrial product have been verified by physical failure analysis that our technique does not lead to wrong diagnosis for single defect cases.

A diagnosis technique based on delay testing has been developed to map the severity of process variation on each cell/interconnect delay. Given this information, we demonstrate a post-silicon tuning method on row voltage supplies (inside a chip) to restore the performance of failed chips. The method uses the performance map to set voltages by either pumping up the voltage on cells with worse delays or tuning down on fast cells to save power. On our test cases, we can correct up to 75% of failed chips to pass performance tests, while maintaining less than 10% increase over nominal power consumption.

Test integration for heterogeneous cores under test has been a challenging problem in a system-on-chip (SoC) design. To integrate heterogeneous cores under test, the test wrapper should be capable of dealing with multiple-clock domain problems, at-speed testing problems, test power problems, etc. In this paper, we propose an alternative wrapper architecture that supports multiple clock domains, and therefore test operations can run (test) at system speed. Since each CUT has very different requirements, the test wrapper unavoidably needs to be re-designed for a new CUT. In order to reduce the manual effort, we propose to automatically generate test wrappers and the corresponding test programs based on the given configuration and test description for each CUT. We adopted the IEEE 1450.6 standard, a.k.a. Core Test Language (CTL), as the test description language in this work. Through the process, circuits can be tested with low overheads, and minimal intervention from designers will be required. We have successfully integrated a test wrapper generated by using our tool into a test chip which includes a Memory BIST and a Logic BIST and tapped out the chip in TSMC 0.18$\mu$m technology. The experiments showed that the area overhead of proposed architecture is only 0.02\% of chip area in the chip.

Diagnosis for delay defects becomes more significant as the CMOS process advances to nanometer regime. The most challenging problems of delay fault diagnosis in nanometer process come from the process variation, which results in small delay variations. Small delay variations are difficult to be diagnosed by using existing methods based on a specific fault model. This paper presents a new estimation method for gate or interconnect delays based on the maximum likelihood estimation. The proposed method outputs most probable gate/interconnect delays that matches the measured path delays under the nominal delay distribution. Unlike the previous diagnosis methods, our method does not take any assumption on defect numbers, sizes and types (models), and thus it can be used to diagnose performance bottlenecks resulted from systematic variations. The experimental results show that the average correlation achieves 0.848 between estimated (by the proposed method) and sampled segment delays (generated from process models) for ISCAS89 benchmarks. There is a substantial improvement of 0.271 over the existing method.

Diagnosis tools can be used to speed up the process for finding the root causes of functional or performance problems in a VLSI circuit. In this paper, we propose a method to locate possible segments that cause extra delays on circuit paths. We use the delay bounds of the tested paths to build linear constraints. By guiding the solutions of the linear constraints solved by a linear programming solver, we can identify segments with extra delays. Also, with the ranks of segment delays, we can prioritize the search for possible locations of failed segments. Besides, we also propose to reduce the search space by identifying indistinguishable segments. Essentially, we cannot separate segments in the same category no matter which segments have faults. This approach greatly increases the efficiency of the diagnosis process. Three main features of the proposed method are that: 1) it does not assume any delay fault model; 2) it derives diagnosis results directly from test data; and 3) it is able to diagnose failures caused by multiple delay defects. These features make our proposed method more realistic on solving the real problems occurring in the manufacturing process. In the experimental results, for most cases of injecting 5% of the longest path delay, the probabilities are over 90% for locating faulty segments within the list of top-ten suspects, and the average rankings, that is often referred to as first hit rank (FHR), which is defined as the rank of the first hit of the defect in the ranking list, are among the top five suspect locations for single fault injection. In the experimental results of multiple faults injection, the average FHRs are also lower than 5 for all cases of injecting 1% of the longest path delay.

Systematic variations with device parameters and critical dimensions are crucial information in achieving higher yields with semiconductor devices. In this paper, we propose a method to extract systematic variation models of segment delays based on the measured path delays of tested chips. First, we cluster chips according to the similarity of the path delay vectors. Then, for each cluster, a hierarchical variation model is built. The extracted models are closely related to the design and can have many potential applications for yield and quality enhancements.

Traditionally, diagnosis methods use static models for delay defects, while there exists a class of faults including cross-coupling capacitance and resistive shorts exhibiting different effects on path delays with different input patterns. Blindly treating such faults will lead to skewed results for locating defects. In this paper, we discuss the method to handle these faults without explicitly modeling each type of faults. In the process, we differentiate failed delay paths into two categories: static and pattern-dependent. We further explore these information to list possible candidates (including coupling defects) causing timing failures for further analysis. The experimental results show that average rankings of suspects are 2.1 and 4.6 for failing segments and coupling pairs, respectively.

Diagnosis tools can be used to speed up the process for finding the root causes of functional or performance problems in a VLSI circuit. In this paper, we proposed a method to locate possible segments that cause extra delays on circuit paths. We use the delay bounds of the tested paths to build linear constraints. By guiding the solutions of the above linear constraints with a linear programming solver, we can identify segments with extra delays. Also, with the ranks of segment delays, we can prioritize the search for possible locations of failed segments. In the diagnosis framework, we also propose to reduce the search space by identifying indistinguishable segments. Essentially, we cannot separate segments in the same category no matter which segments have faults. This approach greatly increases the efficiency of the diagnosis process. In the experimental results, for most cases of injecting 10% of the longest paths delays, the probabilities are over 90% for locating faulty segments within the list of top-ten candidates, and the average rankings are among the top 5 suspect locations.