Designers of complex SoCs have to face the issue of tuning their design to achieve low power consumption without compromising performance. A set of complementary techniques at hardware level are able to reduce power consumption but most of these techniques impact system performance and behavior. At register transfer level, low power design flows are available. Unfortunately, equivalent design flows at transactional level are missing. In this paper we describe how a power/clock intent could be described at transactional level using a separation of concerns process and how the transactional simulation code merging functional and power behaviors can be generated automatically using a model-driven engineering approach.

Dynamic power management (DPM) has become a major technique for reducing power consumption in SoCs. One of the main challenges in DPM is to predict as soon as a component enters in idle mode if it will stay in this mode for a time longer than a minimum value that leads to power savings. Even if a component in power off state does not consume any power, waking up such a component induces a time penalty before it returns in running mode which impacts application performances. Moreover, the activity of components in any architecture depends on the mapping and scheduling of application tasks onto these components. These dependencies cannot be captured if power management decisions are taken on a per-component basis. Therefore, we propose a DPM technique based on a history of global states of the system where a global state is a collection of individual states of components at a given time. As a consequence, observing global state transitions at component level provides relevant information which help in taking decision to power off components and to anticipate their wake-up instants.

Due to the ever-increasing demands on energy efficiency, designers are struggling to construct efficient and correct power management strategies for complex System-on- Chips (SoCs). The validation of an efficient power intent for a SoC is challenging and should be considered at early stage of the electronic system-level (ESL) design flow. To tackle this issue, we propose a high-level modeling approach on top of SystemC/TLM standard allowing the control structure of a power intent to be described in relationship with a functional transaction-level model (TLM) of a SoC. We consider a separation of concern approach in order to make easier the exploration of power intents and the optimization of power consumption. In this paper, the focus is set on an abstract clock intent model through a generic library and a modeling methodology allowing the development of a power management strategy on top of a functional SystemC-TLM model of a virtual prototype. A case study is used to demonstrate by simulation experiments the efficiency of this approach illustrating its capability to analyze effects of power management on performance and power consumption.

In this paper, we propose a global power management approach for energy harvesting sensor nodes. Our approach is based on a joint duty-cycle optimization and transmission power control. By simultaneously adapting both parameters, the node can maximize the number of transmitted packets while respecting the limited and time-varying amount of available energy. We obtain a high-packet delivery by using an original predictive transmission power control that can efficiently adapt the transmission power to the wireless channel conditions. To accurately model the wireless channel and the node communication hardware, a waveform-level radio frequency simulator has been developed. Simulation results show 6.5 times improvement in energy efficiency and a packet reception ratio which is 9 times more efficient than a recently published technique. A 15% increase in energy efficiency, with respect to a fixed transmission power configuration, has also been observed. Finally, the global power management strategy has been validated on a real wireless sensor networks platform. Experimental results are very similar to those obtained in simulations, and thus confirm the efficiency of our power management approach.

A lot of task scheduling algorithms and power management policies have been developed based on simplistic power models, which rarely take into account the effects of the power consumptions of the different components of a real system. Most of the models on which the study of the DVFS scheduling is based, make the assumption that the power consumption of a processor could be modelled as a E ∝ V 2 model. This hypothesis, even if partly true, is not generally applicable when considering the complete system, which consists of the processor, memories and power conversion circuits. In this paper we present a power and energy model for a DVFS enabled mobile computing platform. The platform is based on a low power SoC, which integrates both the processor core and memory, as well as other hardware accelerators. We include in our analisys the study of the power conversion components, which supply the SoC. Starting from measures, we first characterize the power consumption of the SoC and the converters, then a power and energy model for the processor is proposed. The model is able to predict the power consumption of the processor core with an average error less than 10%. This is then used to analyse two DVFS scheduling techniques based on the EDF algorithm, Cycle Conserving and Look Ahead. The results show that the CPU energy saving computed using our model, is far less than what would be expected using a model that does not take into account the effect of the static power.

This paper considers the problem of power/energy minimization for periodic real-time tasks that are scheduled over multiprocessor platforms that have dynamic power management (DPM) and dynamic voltage & frequency scaling (DVFS) capabilities. Early research reports that while both DPM and DVFS policies perform well individually for a specific set of conditions, they often outperform each other under different workload and/or architecture configuration. Thus, no single policy fits perfectly all operating conditions. Instead of designing new policies for specific operating conditions, this paper proposes a generic power management scheme, called the Hybrid Power Management (HyPowMan) scheme. This scheme takes a set of well-known existing (DPM and DVFS) policies, each of which performs well for a given set of conditions, and adapts at runtime to the best-performing policy for any given workload. We performed experiments with state-of the-art DPM and DVFS techniques and results show that HyPowMan scheme adapts well to the changing workload and always achieves overall energy savings comparable to the best-performing policy at any point in time.

The intent of the recent H.264/AVC standard is to provide high quality video at low bit-rates and work effectively on a wide variety of networks and systems. A promising application is video broadcasting on mobile terminals butin practice, increased processing power and power management are required for embedded systems. In this paper, we consider an embedded multiprocessor to answer these requirements. This platform is the ARM11 MPCore, including up to four processors to bring enough processing power with dynamic voltage and frequency scaling techniques (DVFS). We present here the parallelisation and implementation analysis of a H.264 decoder using symmetric multiprocessing. We detail the performance and power consumption of the decoder in different conditions of voltage and frequency in a way to derive information for the exploitation of DVFS techniques in multiprocessor architectures.

Several techniques were developed to reduce processor consumption which was the predominant source of dissipation. However with the technology evolution and the development of new applications that make heavy use of large memory data size, the energy savings obtained by these techniques become limited. In this article we showed that Dynamic Voltage Frequency Scaling technique (DVFS) increases the main memory consumption. A multi-banked memory architecture, having the capability of setting banks in low power modes when they are not accessed, is adopted to reduce the memory consumption. An approach of tasks allocation and banks configuration reducing the memory energy is developed at system level for multi-task and real-time systems. Experimental results show that, when we combined DVFS technique with an efficient multibank architecture and tasks to banks allocation, a system energy saving that reaches 35% is obtained.

In order to minimize the energy consumed by the main memory in embedded systems, several solutions are proposed. An architectural solution is particularly effective in reducing this memory consumption part. It consists of multi-banking the addressing space instead of a monolithic memory. The main advantage in this approach is the capability of independently setting banks in low power modes when they are not accessed, such that only the accessed bank is maintained in active mode. In this paper, the authors investigate how the power management capability built into modern DRAM devices can be handled for real-time and multitasking applications. The authors aim to find, at system level design, both an efficient allocation of application's tasks to memory banks, and the memory configuration that lessen the energy consumption: number of banks and the size of each bank. Experiments show an energy savings of 15% for the considered two benchmarks

In this paper, we present a partitioning methodology targeting a dynamically reconfigurable architecture. We first identify this class of architectures and point out the lack of underlying tools and compiler support exploiting, with these architectures, the potential task level parallelism (TLP). The applications in today's and the future embedded systems are more and more control dominated making necessary the use of a specification that handles jointly treatment and control. Our methodology starts from a system level specification in safe state machines (SSM: the graphical formalism of ESTEREL) integrating task level granularity treatments (as C function calls) in a control flow environment. After simulation and formal proof, we explicitly partition all the different configurations of the SSM i.e. the different combinations of control and treatment that the system has to perform at each operational tick. We also develop a technique that enables to contain the explosion of the number of these configurations and establish the efficiency of our method through its application to a video supervision application and to the JPEG 2000 standard.

We present a new HW/SW partitioning approach. This partitioning method is called an online partitioning algorithm (O.P.A) which consists to adapt dynamically the architecture to the processing requirements. A scheduling heuristic is associated to this partitioning approach. We compare our method with an off-line static HW/SW partitioning approach.

This paper presents a Genetic Algorithm (GA) based approach for Hardware/Software partitioning targeting an architecture composed of a processor and a dynamically reconfigurable datapath (FPGA). From an acyclic task graph and a set of Area-Time implementation trade off points for each task, our GA performs HW/SW partitioning and scheduling such that the global application execution time is minimized. The efficiency of our GA is established through its application to an AC-3 decoder function and its performance is compared with a greedy algorithm.

The increasing complexity of embedded applications combined with the advances in chip integration make the design process a very challenging task. Due to this rising complexity, the design under performance, area and consumption constraints of a system-on-a-chip (SOC) composed of mixed software-hardware units, becomes increasingly intricate. This paper presents a method and an associated tool (CODEF) which allow the designer to do an automatic and/or interactive system design space exploration in order to construct cost effective embedded real-time architectures dedicated to complex signal processing applications. The method is based on a recursive partitioning algorithm followed by a communication synthesis procedure.

The complexity of embedded applications increases continuously. Integration advances provides a rising range of possibilities to implement a system on a chip. The designers are faced to the difficult challenge to select the right units to implement the application functionalities so that the silicon area is minimized and the time constraints of the application are met. This paper presents an effective method to design system architectures which operates on a conditional data flow graph which is well suited to represent signal processing applications.

Continuous advances in processor and ASIC technologies enable the integration of more and more complex embedded systems. Since their implementations generally require the use of heterogeneous resources (e.g., processor cores, ASICs) in one system with stringent design constraints, the importance of hardware/software codesign methodologies increases steadily. Interfacing heterogeneous hardware and software components together through a communication structure is particularly error prone and time consuming. Hence, on the basis of a generic architecute dedicated to telecommunication and multimedia applications, we proposed an extended communication synthesis method that provides characterization of communications and their implementation schemes in the target architecture. This method takes place after the partitioning and scheduling phase and may constitute the basis of a back-end of a codesign framework leading to HW/SW integration.

Generation of optimized DSP code from a high level language such as C is very time consuming since current DSP compilers are generally unable to produce efficient code.We present a software estimation methodology from a C description that helps for a rapid development of DSP applications.Our tool VESTIM provides both a performance evaluation for assembly code generated by the compiler and an estimation of an optimized assembly code.Blocks of applications G.721 and G.728 have been evaluated using VESTIM.Results show that estimations are very accurate and allow software development time to be significantly reduced.

Continuous advances in processor and ASIC technologies enable the integration of more and more complex embedded systems. Embedded systems have become commonplace in recent years. Since their implementations generally require the use of heterogeneous resources (e.g., processor cores, ASICs) in one system with hard design constraints, the importance of hardware/software codesign methodologies increases steadily. HW/SW codesign approaches consist generally of HW/SW partitioning and scheduling, constrained code generation, and hardware and interface synthesis. This article presents the codesign of an industrial experiment in acoustic echo cancellation (GMDFα algorithm); and emphasizes the partitioning and communication synthesis steps. This experiment brings to light interesting problems such as data and program distribution between system memories and the modeling of communications in the partitioning process

In this paper, a synthesis method of dedicated architectures is introduced. Its aim is to produce optimized systems derived from the algorithmic expression of a numerical application. The approach addresses the design of dedicated systems for applications that require high numerical computations. An efficient utilization of hardware resources is achieved through the use of vector processing with an SIMD implementation. The synthesis algorithm realizes simultaneously the design of SIMD structures and the generation of the microcode needed for implementing a software pipelining of operation of the input program.>

A multiprocessor machine with two operating modes and simple synchronization mechanisms is discussed. The operating modes are the vector single-instruction multiple-data (SIMD) mode and the parallel single program stream, multiple data stream (SPMD) mode. Synchronizations are reduced to the switching between these two modes. Mixing these two operating modes offers the programmer a comfortable programming environment: vector parallelization is performed by the compiler and the hardware, and, since SPMD parallelization requires mainly the partitioning of the entire set of data, the synchronizations are then often obvious.>

Some results of the CAPSYS method are presented. It is a new high-level synthesis method whose objective is to benefit from very long induction word (VLIW) compilation and digital signal processor (DSP) synthesis experiences to generalize the automatic processor design process. The major characteristic of this approach is to synthesize architecture in a global way. Instead of a single operative area, the synthesis considers a complete architecture. It permits one to take into account memory throughput, for instance, and, more generally, exchanges with the environment of the synthesized processor. The first part of the method, the generation of architectural models, is emphasized. This procedure furnishes a full spectrum of architectural decompositions (i.e. the number and the type of the functional units) from maximally parallel ones to fully serial ones. In each one, the synthesis algorithm creates an adequacy between the machine and the microcode. Results showing the influence of memory management on synthesized processors are given.>

The partitioning/scheduling/allocation algorithm developed for the CAPSYS method is presented. The aim of this project is to define a tool able to automatically design dedicated and embedded VLIW architectures for large and complex applications. It inherits a sizable knowledge-pool from the wider field of parallel processors, VLIW compiler design and high-level synthesis. Emphasis is placed on constraints of such a system synthesis approach and more especially on the particularity of the partitioning step. The proposed solution implements a software/hardware approach based on the list-scheduling heuristic.>

OPSILA, is a description given of a general-purpose parallel architecture with two different forms of parallelism: the well-known SIMD (single-instruction, multiple data shown), a synchronous form of parallelism; and SPMD (single program, multiple data stream), which is an asynchronous mode. It is shown that OPSILA is efficient for a wide variety of image algorithms including low and high level processing. The efficiency of OPSILA is demonstrated for the low-level algorithms, through the implementation of a set of typical operations: local (convolution), global (histogram), and geometric corrections.>

There is a continuing pressure of better processing performances in numerical signal processing. Effective utilization of LSI semiconductor technology allows the consideration of multiprocessor architectures. The problem of interconnecting the components of the architecture arises. In this paper we describe a control algorithm of the Benes interconnection network in a asynchronous multiprocessor system. A simulation study of the timeshared bus, of the omega network, of the Benes network and of the crossbar network gives a comparison of performances.