We present a compact model that provides a quick estimation of the stress and mobility patterns around arbitrary configurations of Through-Silicon Via's (TSVs). No separate TCAD simulations are required for these configurations. It estimates nFET and pFET mobility for industry-standard as well as for (100)/substrate orientations. As the model provides mobility info in less than 0.1 millisecond/transistor/TSV, it is possible to be used in combination with layouting tools and circuit simulators to optimise layouts of circuits for digital and analog applications. The model has been integrated into the 3D PathFinding flow, for steering 3D IO placement during stack definition.

One of the problems while simulating heterojunction devices is the poor numerical stability due to the broad number range for concentrations and currents in the different materials. However, it is not obvious which scaling to apply as more than one material is involved. This paper presents a unified scaling system which circumvents the problem. This includes not only the extension of the general de Mari scaling but also an extra scaling with respect to local carrier concentrations. The idea provides a way to deal with the great number range of e.g., the carrier concentrations at heterojunctions. The developed algorithm is very efficient as the new scaling system can also be applied for bulk nodes without altering it. Finally, some examples prove the technique to be very stable and promising for future development.>

For custom integrated circuit design, the use of a reliable device model parameter set as input for the circuit simulator is very important. The curve fitting algorithm in our parameter extraction program SIMPAR is based on a modified Marquardt fitting routine for nonlinear least squares. Classical parameter extraction programs rely only on the minimization of the relative current deviation. But, especially in analog applications (e.g., gain), a correct value for the slope of the I /sub ds/ - V /sub ds/ curves in the saturation region is at least equally important. The new generalized error criterion implemented in SIMPAR extracts a parameter set which minimizes both the current and slope residuals in every point. In doing this, the accuracy of the output conductance modeling has improved considerably, and in some cases even the current residual itself decreases. Although any analytical current-voltage relationship can be used, the SPICE MOS level 3 was chosen as a test vehicle. To illustrate the effect of this new fitting strategy, the gain of a CMOS invertor was calculated.