The energy consumption of a system depends upon the hardware rutd software component of a system.Since it is the software which drives the hardware in most systems.decisions taken during software design has significant impact on the energy consumption of the processor.The paper focuses on decreasing energy consumption of o processor using software techniques.A novel compiler technique is proposed which Educes energy consumption by proper register labeling during the compilation phase.The idea behind this technique is to reduce the energy of the processor by reducing the energy of the instruction register (also the instruction data bus) and the register file decoder by encoding the register labels such that the sum of the switching costs between all the register labels in the tmnsition graph is minimized.There is no hardware pen&y since this is purely a compiler optimization.Results on benchmarks show that the energy consumption of the DLX processor can be.reduced by 9.82% (maximum) and 4.25% (avenge) (as measured by DLX energy simulator).In addition seveml compiler techniques such os loop unrolling, software pipelining, recursion elimination and of effects of different algorithms on power and energy consumption are studied.This evaluation methodology is usefid for computer architects to evaluate energy improvements of their hardware, compiler writers to evaluate energy of the compiled code nnd program writers to evaluate energy of data structures and algodhltls.v---e.?_ .

We illustrate a new method to characterize the energy dissipation of circuits by collapsing closely related input transition vectors and energy patterns into capacitive coecients.Energy characterization needs to be done only once for each module (ALU, multiplier etc.,) in order to build a library of these capacitive coecients.A direct high-level energy simulator or pro ler can then use the library of pre-characterized modules and a sequence of input vectors to compute the total energy dissipation.A heuristic algorithm which performs energy clustering under objective constraints has been devised.The worst case running time of this algorithm is O(m 3 n), where m is the number of simulation points and n is the number of inputs of the circuit.The designer can experiment with the criterion function by setting the appropriate relative error norms to control the `goodness' of the clustering algorithm and the sampling error and con dence level to maintain the suciency of representation of each cluster.Experiments on circuits show a signi cant reduction of the energy table size under a specied criterion function, cluster sampling error and con dence level.

Gray code addressing is one of the techniques previously proposed to reduce switching activity on high capacitance address bus lines. However in order to convert a system to gray address encoding there are several issues a designer needs to consider. This paper analyzes two issues which include gray code encodings for counter increments other than one and tradeoffs in power consumption incurred due to code conversions (binary to gray, gray to binary) when considering address increments and adders. Results are shown for different encodings and different configurations.

This paper describes a method to model the software component of energy dissipation from an architectural description of an embedded system. An embedded system is characterized by a dedicated processor (a DSP processor or an "off the shelf" microprocessor) and the application specific software that runs on it. The hardware model of the system consists of several interacting modules (e.g. ALU, register file, controller etc.). A black box model of a cell from each module is built which consists of a table of switching capacitances (from IRSIM-CAP) for each combination of previous to present input transitions. Using this black box cell model and the past and present inputs to the module it is possible to accurately calculate the energy dissipation of the module. By performing a simple "bookkeeping" operation of all the modules activated during the instruction, it is possible to exactly estimate the energy dissipation of an instruction. A power profiler (PPROF) is built which takes as an input the program and the model of the basic units of each module and profiles the energy for each instruction of the program. In addition, it also outputs the energy consumption statistics for each type of instruction and for each module. A programmable microprocessor with sixteen instructions has been designed, and programs written for this machine are analysed using PPROF. The results of the estimated instruction energy are within 8% maximum error when compared with IRSIM-CAP.

Several techniques to estimate power consumption o f a combinational circuit using probabilistic methods have been proposed.However none of these techniques take i n to account circuit activity when two o r more inputs change simultaneously or when glitching occurs.A formulation is presented in this paper which includes signal correlation and multiple gate input switching.Work is also presented in estimating the glitching contribution to the switching activity.Results obtained from benchmarks and test circuits show v ery good accuracy when compared to actual activities as measured by SPICE and IRSIM.