Artificial intelligence (AI) has surpassed top human players in a variety of games. In imperfect information games, these achievements have primarily been driven by Counterfactual Regret Minimization (CFR) and its variants for computing Nash equilibrium. However, most existing research has focused on maximizing payoff, while largely neglecting the importance of strategic diversity and the need for varied play styles, thereby limiting AI’s adaptability to different user preferences. To address this gap, we propose Preference-CFR (Pref-CFR), a novel method that incorporates two key parameters: preference degree and vulnerability degree. These parameters enable the AI to adjust its strategic distribution within an acceptable performance loss threshold, thereby enhancing its adaptability to a wider range of strategic demands. In our experiments with Texas Hold’em, Pref-CFR successfully trained Aggressive and Loose Passive styles that not only match original CFR-based strategies in performance but also display clearly distinct behavioral patterns. Notably, for certain hand scenarios, Pref-CFR produces strategies that diverge significantly from both conventional expert heuristics and original CFR outputs, potentially offering novel insights for professional players.

This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effects created by high-power analog circuits and affecting sensitive digital circuits on the same integrated circuit. The sources and mechanism of the noise behavior of such digital circuits are identified and analyzed. The results are obtained primarily from a set of dedicated test circuits specifically designed, fabricated, and evaluated for this work. The conclusions drawn from the theoretical and experimental analyses are used to develop physical and circuit design techniques to mitigate the substrate noise problems. These results provide insight into the noise immunity of digital circuits with respect to substrate coupling.

Theoretical, simulation and experimental analysis and data are presented, discussing physical design techniques which influence the noise behavior of digital circuits in a mixed-signal smart-power system. Several physical design strategies are presented to improve the noise immunity of digital circuits in smart-power systems.

Experimental data describing circuit and physical design issues that influence the noise immunity of digital latches in mixed-signal smart power circuits are described and discussed. The principal result of this paper is the characterization of the conditions under which substrate noise generated by high power analog circuitry affects digital latches. The experimental data characterize a variety of different noise mitigation techniques for the particular process technology circuit structures, signal/clocking interdependencies, and related conditions.