This paper explores a robust and computationally efficient soft-output fixed-complexity sphere decoder (FSD) designed for large-scale multiple-input multiple-output (MIMO) detection. A partial expansion strategy is designed for the first two layers of the proposed FSD, utilizing enumeration orders for both the real and imaginary components of the signal space. Additionally, a section-wise list candidate selection method, incorporating an innovative grouping strategy, is specifically designed for the leaf layer. These techniques complement each other to significantly reduce computational complexity and minimize processing delays. Furthermore, log-likelihood ratio (LLR) refinement is implemented to counteract overestimation caused by the bit-flipping algorithm, leading to notable improvements in error performance. Simulation results demonstrate that the proposed soft-output FSD achieves superior error performance compared to benchmark schemes and approaches the list sphere decoder, while maintaining significantly lower complexity.

This paper presents a method for blind carrier frequency offset (CFO) estimation for quadrature amplitude modulation (QAM). Our proposed algorithm has three major steps, including two-stage full modulation removal, symbol aggregation, and iterative parabolic interpolation. In the first step, a preliminary CFO estimate will be evaluated using the QPSK sub-constellations. The modulation values of the remaining constellation points are partially removed based on the preliminary CFO estimate, and the residual modulation values are quantized to achieve the full modulation removal. In the second step, modulation-removed symbols are paired and weighted based on their reliability levels. This symbol aggregation step improves the estimation accuracy and reduces the FFT size of the following FFT-based CFO estimation. A trade-off between performance and complexity can be achieved by adjusting the aggregation length. In the final step, an iterative parabolic interpolation technique is introduced to mitigate the estimation bias. Performance evaluation shows that the proposed method provides better mean square error (MSE) performance and comparable complexity compared to the existing CFO methods for QAM.

In bit-interleaved coded modulation (BICM) systems, the conventional demodulation assumes equal a priori probabilities for all constellation points, inherently leading to performance degradation. To enhance the performance of BICM, BICM with iterative decoding (BICM-ID) was developed. We aim to apply neural networks to BICM to achieve joint modulation and decoding and overcome the performance degradation, with the goal of surpassing the performance of BICM-ID. In this paper, we propose a neural demodulator that incorporates an additional probability layer to mitigate performance degradation in BICM systems. Furthermore, we introduce Joint Model-1, which integrates this neural demodulator with a belief propagation (BP) decoder for 16-QAM polar-coded BICM. To further improve performance, we use Joint Model-1 as a pre-trained model and extend it by adding an additional dense layer, resulting in Joint Model-2. Experimental results show that Joint Model-2 surpasses both BICM and BICM-ID systems under Ungerboeck labeling.

The eBCH-polar codes is a powerful way to construct polar codes. With high minimum Hamming distance, it outperforms ordinary Polar codes under successive cancellation list (SCL) decoder. However, the absence of cyclic redundancy check (CRC) bits in eBCH-polar codes makes it challenging to adopt SCL-flip (SCLF) decoding scheme. In this research, we propose a flip scheme activated by a Normalized Path Metric (PM) range and a mismatch criterion, which respectively leverage the properties of SCL decoding and dynamic frozen bits of eBCH-polar codes. This work also improves the selection the flipping bits by modifying metric to account for the structure of dynamic frozen bits and reduce the search space. Based on these modifications, we proposed SCLF-1 and SCLF-2 decoding algorithms for eBCH-polar codes. Simulation results show that both of the proposed decoding schemes achieve superior performance compared to other contemporary decoding algorithms for CRC aided polar (CA-polar) codes, demonstrating enhanced error rates performance within the same decoding attempt.

Although belief propagation (BP) decoders are efficient and provide significant performance for classical low-density parity-check (LDPC) codes, they will suffer a degradation in performance for quantum LDPC (QLDPC) codes due to the limitations in the quantum field. In this paper, we propose a posterior adjustment of either a single qubit or multiple qubits within binary BP. The adjustment process changes the posterior likelihood ratio for one or multiple qubits according to the designed criterion. Simulations show the performance of both single and multi-qubit adjustment is able to outperform the conventional binary BP decoder and also outperform the BP decoder concatenated with the zero-order ordered-statistics decoding (BP+OSD-0). Moreover, with lower complexity, the performance when using our proposed decoder on the considered QLDPC codes can be close to high-order OSD.

Quantum computing requires an error correction code to protect the messages against quantum noise. Surface codes are suitable for quantum error correction based on their local-qubit connection. Decoding via the conventional belief propagation (BP) algorithm is deficient for highly degenerated codes. Using the proposed block-layered sign-flipping (SF) technique, this problem can be mitigated and the error rate performance can be improved. The decoder hardware implemented for the [181, 1, 10] surface code occupies an area of 0.97 mm2and achieves a latency of 315 ns in a 90 nm process.

In recent years, neural network decoding of polar codes, such as neural belief propagation (BP), has been intro-duced. These methods use deep learning to transform the factor graph into a neural network model by unfolding the decoding iterations, thereby enhancing the accuracy of traditional decoding processes. However, current prevalent methodologies for loss function calculation only take into account the output of the final layer. In our analysis, we found that when calculating the loss function using only the output from the last layer, the convergence speed of the decoder significantly decreases, especially when the number of unfolded iterations is higher. In this paper, we incorporate the output of all iterations into the loss function in the original neural BP structure. Additionally, we optimize the loss function by assigning different weights to losses at different iterations. As a result, the weighted loss function not only provides a lower Bit Error Rate (BER) compared to the original neural BP decoder at lower SNR, but also accelerates convergence speed.

This paper presents two methods for blind carrier frequency offset (CFO) estimation for amplitude phase shift keying (APSK) signals. The first approach carries out modulation removal using the outermost symbols of APSK and then utilizes an iterative parabolic interpolation technique to mitigate the bias of FFT-based CFO estimation. The second method conducts two-stage full modulation removal and aggregates symbols to reduce the FFT size for CFO estimation. In the symbol aggregation process, modulation-removed symbols are paired and weighted based on their reliability to achieve accurate estimation. The first method demonstrates better performance, particularly for high-precision requirements, while the second method offers a more adaptable trade-off between performance and complexity by adjusting the aggregation length. Both methods are more efficient and provide better mean square error (MSE) performance compared to existing ones. Moreover, numerical complexity analyses show the efficiency of the proposed algorithms.

In this paper, two improvements for successive cancellation list flip (SCL-Flip) decoding are presented for polar codes. First, a novel bit-selection metric based on path metric (PM) is introduced. With the proposed metric, the improved scheme can have lower complexity and saturate faster than other state-of-the-art decoders. Second, we generalize the SCL-Flip decoding, denoted SCL-Flip-ω, to flip the decision in path competition at most ω times in decoding process. We analyze the frequency of channel-induced error under various circumstances, measure the trade-off between error-correction performance and complexity, and then propose SCL-Flip-2 decoding which is the first SCL-based decoding that allows for multiple bits for flipping to the best of our knowledge. Simulation results reveal that the proposed decoding with a small list size can achieve a better performance than CA-SCL decoding with a large list size while keeping the complexity low.

In order to minimize the decoding period and the response time for Polar Codes, an early termination (ET) scheme based on additional check points (ACPs) is proposed in this work. For conventional ET schemes based on distributed parity-check (PC) bits, ET can only be triggered when the decoding process reaches the PC bits. The ACPs are selected from the information bits, and extend the feature of the PC bits, where ET can also be triggered at the ACPs, meaning that a more rapid ET is available that does not impact the error-rate performance. With sophisticated method of selecting ACPs based on the channel-independent polarization weight (PW), the proposed ET scheme is able to reduce the response time by about 5.

By knowing the future price range, which is the difference between the closing price and the opening price, we can calculate the long or short positions in advance. This paper presents a Recurrent Neural Network (RNN) based approach to forecast the price range. Compared to other methods based on machine learning, our method puts greater focus on the characteristics of the stock data, such as the zero-crossing rate (ZCR), which represents the ratio where the sign of the data changes within a time interval. We propose a decision-making method based on an estimate of the ZCR to enhance the ability to predict the stock price range, and apply our method to the Standard & Poors 500 (S&P500) stock index. The results indicate that our method can achieve better outcomes than other methods.

This paper presents hardware-friendly LDPC decoding schedules for 5G hybrid automatic repeat request (HARQ) applications. Since there are built-in punctured blocks in the parity check matrix (PCM), a scheduling technique is proposed that allows the punctured nodes to be efficiently recovered. For HARQ using the Chase combining (CC), the previous decoding results corresponding to the punctured part are retained, and the proposed layered decoding is arranged according to the row weight. For HARQ using the incremental redundancy (IR) approach, the parity bits corresponding to the pure-row-orthogonal part of the PCM are transmitted first. The hardware implementation shows that the throughput can be increased by 21.37% for the first decoding attempt, 56.9% for CC-HARQ and 14.51% for IR-HARQ when the code rate reaches 0.303.

In Asian countries, seals are widely used for authenticating the identity of a person or organization. Therefore, the ability to efficiently verify whether a seal is either genuine or forged is important. We propose an effective method of verification based on Hough transformation to approximate the imprint borders and the four vertexes, and use geometric transformation to align the perspective of the detected imprint image with the genuine imprint. After the edge-difference images between the original image and the detected image are created, distance transformation and connected-component labeling are applied. Finally, the number of edges in the connected component and the distance to the closest point in the edge of original image are used to calculate the input vector for the SVM (support vector machine). The imprint is then determined to be either genuine or forged. The experimental results show the effectiveness of the proposed verification approach.

In previous studies, a very sparse low-density parity-check (LDPC) code was designed for triple-level cell (TLC) NAND flash using non-Gray mapping, which is able to achieve comparable error-rate performance to the conventional Gray mapping-based scheme. Although a sparse LDPC code can be of benefit to hardware implementations of an iterative demodulation and decoding (IDD) scheme, difficulties emerge, such as latency issue between the decoder and demodulator, when compared to non-IDD schemes. In this paper, a hardware-friendly structure interleaver is used such that a shuffle-based IDD scheme can be realized efficiently. Compared to the conventional Gray-based non-IDD scheme and layered-based IDD scheme, the proposed shuffled-based IDD scheme can provide a better hardware efficiency and better error-rate performance.

In this paper, spatial coupling technique is used to improve the error-correcting performance of finite length polar codes. Polar codes are considered as base codes of coupling. Two types of spatial-coupling methods are investigated. For the first coupling method, some message bits of a polar base code at each coupling position are used as frozen bits of one-side adjacent polar base code. For the second spatial-coupling method, multiple polar codes are associated by combining message bit blocks of adjacent coupling positions with modular-two addition. Simulation results show that, with a little extra iteration complexity, the two types of spatially coupled polar codes can provide better error-correcting performance than original polar codes. When setting the coupling ratio at 0.33 and coupling pattern as Uncertain-Certain, the first spatial-coupling method provides the best performance output. The second spatial-coupling method with coupling width 3 provides better performance than that with coupling width 2. Furthermore, the first spatial-coupling method with short message block length provides better decoding performance, and the second method with large message block length performs better.

This paper proposes an iterative soft-decision decoding algorithm for Reed-Solomon (RS) codes. The proposed decoding algorithm combines the concepts of adapting the parity-check matrix and informed dynamic scheduling decoding. The parity-check matrix is re-arranged before each iteration, where the systematic part is mapped to the least reliable bits, consequently reducing their influence on the other bits. Using dynamic scheduling, the more important decoding messages are updated to these least reliable bits, meaning that the majority of the error bits with low reliability can be corrected. When the proposed integrated decoding is applied to (255, 239) RS code, the difference between its frame error rate performance (FER) and the maximum-likelihood (ML) bound can be reduced to 0.8 dB, and a gain of about 0.1 dB is achieved compared to all the previously recorded soft-decision decoding for RS codes.

In this paper, a coded modulation scheme using extremely sparse low-density parity-check (LDPC) codes is proposed for the stored signal of triple-level-cell (TLC) NAND flash, where both the encoding and the decoding complexity can be significantly reduced with the advantage of the extremely sparse code graph. In order to enhance the performance of decoder, iterative detection decoding (IDD) is introduced to extract the extrinsic information from the symbol detector, and the cooperative non-Gray mapping is also designed. In addition, for error floor lowering, an interleaver is inserted to ensure the cascaded degree-2 variable nodes are separated to individual symbols. The simulation results show that the proposed coded modulation scheme can provide a practical error floor performance with a low decoding complexity.

In this paper, we investigate a Raptor-coded distributed noncoherent scheme based on a non-orthogonal spacetime modulation (NOSTM) signal and a dynamic decode-and-forward (DF) relaying scenario. The distributed NOSTM signal is firstly proposed based on unitary space-time modulation (USTM) and spatial multiplexing (SM). The dynamic DF relaying protocol is investigated to process the non-orthogonal feature of the NOSTM signal. A Raptor-coded distributed scheme is then constructed for the relay network, and the corresponding transmission and reception procedures are also investigated. It is shown that the throughput performance can be effectively improved, especially for cases when the location of the chosen relay nodes is distant from the source node.

Low-density parity-check convolutional codes (LDPC-CCs) are generally decoded using sliding- window based message passing decoding. Based on the sliding-window decoding, an informed dynamic scheduling (IDS) for LDPC-CC is proposed in this work, where the decoding convergence can be significantly accelerated. Since the number of processors required for a satisfactory performance can be reduced, the decoder can be simplified. A set of rate-compatible (RC) puncturing patterns is also proposed and is used to construct RC LDPC-CCs for the performance evaluation of the proposed IDS. Although the proposed puncturing pattern cannot be optimized for individual code rate owing to the rate-compatible constraint, they can still provide a comparable error rate performance compared to the codes defined in the IEEE 802.16m standard. It is worth noting that these standard codes are not rate-compatible.

It is known that by extracting log-likelihood ratio (LLR) values from the received MIMO signals, a MIMO detector is able to exchange a posteriori soft information with a channel decoder to improve the error performance. A minimum mean-square error with parallel interference cancellation (MMSE-PIC) detector is considered to be a practical MIMO detector, but the computational complexity for the LLR computation is still at a high level for higher-order modulations. This paper presents a low-complexity LLR computation algorithm together with the hardware implementation for MMSE-PIC detectors. The complexity is evaluated using logic synthesis based on a 90-nm CMOS technology. For 256-QAM modulation, a 50% reduction in area is achieved. In addition, a 44% reduction in area can be achieved for a multi-mode MMSE-PIC detector that supports multiple modulations for signals up to 256-QAM.

By using stochastic computation, a fully-parallel low-density parity-check (LDPC) decoder can be implemented using a lower wire complexity. In order to enhance the decoder performance, probability tracers, such as up/down counters, are added at each edge between variable nodes and check nodes, as described in previous literature. However, this causes a large decoding latency and a high number of decoding failures. In this paper, a convergence-optimized structure for variable nodes is proposed that is able to overcome these issues. As a result, the throughput for the proposed decoder is 20.5Gb/s, which is 101% higher than the original counter-based decoder presented in the previous literature.

This paper shows that the decoding convergence of the punctured low-density parity-check (LDPC) codes can be significantly increased using edge wise scheduling belief-propagation. If rate- compatible (RC)-LDPC codes constructed based on puncturing are considered, the maximum mutual information increase (M^2I^2)-based algorithm can be used to arrange fixed schedules for incremental decoding, and further reduce the required number of iterations. With the assistance of the proposed decoding schedules, the puncture-based RC-LDPC codes can be a potential solution for delay- sensitive HARQ (Hybrid-Automatic Repeat reQuest) applications.

Stochastic decoding can be applied to Low-Density Parity-Check codes in order to achieve high throughput with less area. However, most architectures suffer from large decoding latencies, due to the mechanism of stochastic computation. In this paper, three novel strategies, including the LUT-based initialization, the posterior-information-based hard decision and the Bit-Flipping-based post processing, are proposed in order to reduce decoding latency and hence improve throughput. For the standard IEEE 802.3an (2048, 1723) code, simulation indicates 75.7% reduction in average decoding cycles at 4.5 dB with satisfied bit error rate. Moreover, hardware implementation shows that the area of variable node units is reduced significantly in SMIC 65 nm technology.

In this paper, an iterative soft-decision decoding algorithm is proposed for Reed-Solomon (RS) codes. The proposed decoding algorithm combines the concepts of adapting the parity-check matrix and informed dynamic scheduling. Before each iteration, the parity-check matrix is re-arranged according to the reliability of the codeword bits, meaning that the influence of the least reliable variable nodes on the decoding process can be reduced. Consequently, the important decoding messages can be scheduled to be updated first, and the reliability of the least reliable bits can be enhanced. The simulation results show that the proposed decoding algorithm can provide significant improvement in the error-rate performance. By using the proposed algorithm, a gain of 0.5 dB can be achieved compared to the conventional adapting belief propagation algorithm.

In this paper, we investigate Raptor-coded distributed unitary space-time modulation (USTM) schemes, where both the amplify-and-forward (AF) and decode-and-forward (DF) relaying scenarios are considered, under a wireless relay network with arbitrary path gains for the channel fading coefficients. First, the AF and DF relaying procedures are investigated based on the use of an inner USTM signal and an outer Raptor code, and the related noncoherent detectors are also derived. The constellation search for the USTM signal, as well as the optimization for the Raptor code, is then investigated in order to enhance the system performance. It is shown that the designed systems effectively approach the predicted limit in throughput performances and outperform the noncoherent distributed MIMO scheme reported in the previous literature.

This paper presents an efficient min-sum-based decoder for high-rate low-density parity-check (LDPC) codes, where the first minimum and second minimum values are stored in registers. In order to meet a strict cost requirement imposed by NAND flash applications, we provide different upper limits for the first and second minimum values. Furthermore, we use non-uniform quantization for the second minimum value so as to reduce storage complexity. In order to enhance the error-rate performance, the normalization factor is determined based on the difference between the first two minimum values. Using the proposed techniques, a reduction in gate count of 13.36% can be achieved without suffering any degradation in error-rate performance. The implementation results for a rate-0.896 length-18624 layered decoder show that this decoder can achieve a throughput of 765.24 Mb/s at a clock frequency of 166 MHz with a gate count of 620K.

In this paper, we investigate differential amplitude/ phase modulation (APM) schemes for correlated Rayleigh fading channels. Considering the noncoherent maximum-likelihood receiver, a theoretical pairwise error probability (PEP) formula for differential signal vectors with arbitrary power values is derived. The design criterion for the signal set of differential vectors is then proposed based on the asymptotic analysis of the PEP. For both uncoded and coded APM schemes, the design criteria and optimization procedures for bit labeling rules are investigated. The designed differential APM schemes are shown to provide significant improvement in bit-error-rate performance, particularly in the error-floor regions.

This paper presents a maximum mutual information increase (M2I2)-based algorithm that can be used to arrange low-density parity-check (LDPC) decoding schedules for faster convergence, where the increase is used to guide the arrangement of the fixed decoding schedule. The predicted mutual information for the messages to be updated is used in the calculation of the increase. By looking ahead for several decoding stages, a high-order prediction can be realized, which can then be used to devise a schedule with an even faster convergence. For a single received frame, different decoding results can be obtained using different schedules, and, hence, schedule diversity, that lowers the error floor resultant from the dominant trapping sets, is proposed. By adopting the M2I2-based schedule together with the schedule diversity, both the convergence speed in the waterfall region and the error-rate in the floor region can be improved.

After the publication of the residual belief-propagation (RBP) algorithm, many low-density parity-check (LDPC) decoders using informed dynamic scheduling (IDS) have been investigated. In this paper, we propose the twofold-RBP (T-RBP) decoder that combines two residuals. Using T-RBP, significant improvement can be achieved in both convergence speed and convergence error-rate performance. In addition to T-RBP, the simplified-RBP (S-RBP) decoder is also proposed in order to reduce the complexity. Instead of comparing all the residuals of all edges in the code graph, as with previous IDS decoders, S-RBP only compares the residuals of the edges connected to a single check node, thus dramatically reduces the complexity without any significant degradation in performance. The proposed T-RBP and S-RBP can improve not only the performance of dedicated codes, but also that of punctured codes, especially the convergence speed. The improvement can make punctured LDPC codes more practical and becoming a competitive candidate for the rate compatible applications.

In this paper, we focus on the design of differential amplitude/phase modulation schemes by a look-up table for Rayleigh fading channels. In the first part of this paper, we first propose the noncoherent distance measure for each two signal vectors based on the maximum-likelihood (ML) signal detection under Rayleigh fading channels. The design criterion/procedure of the look-up table is then investigated. In the second part of this paper, linear dispersion codes are used to construct a multi-dimensional differential amplitude/phase modulation scheme, with the aid of the genetic algorithm. Both schemes are shown to provide improvements in error performance, when comparing to the conventional scheme provided in the literature.

In this paper, a full-duplex compress-and-forward (CF) protocol for cooperative communication systems using Raptor codes is first investigated. It is verified that the throughput of the full-duplex CF protocol is superior to that of the full-duplex decode-and-forward (DF) protocol when the relay-to- destination channel has a much higher quality compared to the source-to-relay channel, while the full-duplex DF protocol works more effectively than the full-duplex CF protocol in the reverse situation. A full-duplex adaptive relaying protocol that is devised based on both CF and DF protocols is then proposed. In the proposed protocol, the CF and DF protocols are adaptively switched, depending on the channel conditions of the wireless links. In addition, the throughput of the overall system is enhanced using an outer Raptor code. Simulation results show that the proposed scheme smoothly switches between the two conventional protocols to cope with different channel conditions.

In the encoding of Luby transform (LT) codes, information bits (variable nodes) are randomly connected to the check nodes. Although the check-node degrees have been optimized for error-rate performance, the arbitrary connections in the code graph cannot guarantee efficient propagation of the channel information (intrinsic messages), and may slow down the convergence speed of the iterative decoding. This paper presents a design for a generator matrix such that the intrinsic messages can be efficiently propagated through the arranged connections. In addition, the convergence speed of rateless codes can also be accelerated using the proposed degree-oriented scheduling (DOS), where the intrinsic messages are propagated based on the order of check node degrees. An improvement in the convergence speed can be achieved without sacrificing the error-rate performance. In the case of Raptor codes, the BER performance can be significantly improved.

In this paper, we investigate noncoherent transmission schemes using amplitude/phase modulation. For uncoded transmission schemes, we derive the pairwise error probability (PEP) and its high-SNR approximation for signal vectors with unequal power values using a noncoherent maximum-likelihood detector under Rayleigh block fading channels. For coded transmission schemes, we consider differential amplitude/phase modulated signals and introduce a codeword-interleaving strategy to improve the error performance. The design criteria for the signal labelling and bit interleaving are also derived via the high-SNR approximation of the PEP. At the receiver, we devise an iterative channel amplitude estimator to enhance the detection reliability. With the help of a specially-designed iterative receiving algorithm, the designed noncoherent coded scheme can provide a significant improvement, either in the error-floor or the waterfall region.

When residual belief-propagation (RBP), which is a kind of informed dynamic scheduling (IDS), is applied to low-density parity-check (LDPC) codes, the convergence speed in error-rate performance can be significantly improved. However, the RBP decoders presented in previous literature suffer from poor convergence error-rate performance due to the two phenomena explored in this paper. The first is the greedy-group phenomenon, which results in a small part of the decoding graph occupying most of the decoding resources. By limiting the number of updates for each edge message in the decoding graph, the proposed Quota-based RBP (Q-RBP) schedule can reduce the probability of greedy groups forming. The other phenomenon is the silent-variable-nodes issue, which is a condition where some variable nodes have no chance of contributing their intrinsic messages to the decoding process. As a result, we propose the Silent-Variable-Node-Free RBP (SVNF-RBP) schedule, which can force all variable nodes to contribute their intrinsic messages to the decoding process equally. Both the Q-RBP and the SVNF-RBP provide appealing convergence speed and convergence error-rate performance compared to previous IDS decoders for both dedicated and punctured LDPC codes.

As part of the tradeoff between error performance, decoding complexity and the overhead of rateless codes, the combination of incremental decoding (ID) and informed dynamic scheduling (IDS), known as IDIDS (incremental decoding with informed dynamic scheduling), is an attractive solution in binary symmetric channels (BSC). However, applying IDIDS in the AWGN (additive white Gaussian noise) channel may cause a degradation in BER performance, since the incrementally received symbols from the AWGN channel may not be immediately utilized in the decoding process directed by IDS. In addition, a stopping criterion combined with IDS may cause the current decoding attempt to terminate too early, and the channel information contained in the originally received codeword will not be used efficiently. In this paper, a dynamic decoding schedule strategy is proposed. In the proposed decoder, the new received symbols can be immediately utilized in the decoding process. For Luby transform (LT) codes and Raptor codes over the AWGN channel, the proposed algorithm provides a more balanced tradeoff. In the case of Raptor codes, the BER performance is obviously improved.

In this paper, a low-density parity-check (LDPC) coded recording system is investigated, for which the run-length-limited (RLL) constraint is satisfied by deliberate flipping at the write side and by estimating the flipped bits at the read side. Two approaches are proposed for enhancing the error performance of such a system. The first approach is to alleviate the negative effect of incorrect estimation of the flipped bits by adjusting the soft information. The second approach is to increase the likelihood of the correct detection of flipped bits by designing a flipped-bit detection algorithm that utilizes both the RLL constraint and the parity-check constraint of the LDPC code. These two approaches can be combined to obtain significant improvement in performance over previously proposed methods.

In this paper, we present a turbo coded space-time modulation scheme for noncoherent block fading channels, where neither the transmitter nor the receiver knows the channel state information. The turbo coded bits are divided into two parts which are respectively transmitted through information-bearing pilots and spatial multiplexing (SM). Since this approach effectively increases the cardinality of the set of possible transmit (space-time) signal matrices, a large rate gain can be obtained without increasing the modulation order, as shown through achievable-rate analysis. At the receiver, an iterative detection-decoding algorithm is performed cooperatively among the turbo decoder, the coherent demapper for the SM, and the noncoherent demapper for the information-bearing pilots through the help of the proposed signal matrix detector, which enables these two demappers to utilize the channel information inherent in all the received symbols within the same fading block. Compared to the previous work in the literature, the proposed scheme can provide advantages in both error performance and complexity.

For the implementation of low-density parity-check (LDPC) decoders, the associated error performance and the complexity are significantly affected by the number of quantization bits used. In this paper, we propose an adaptive quantization scheme, which uses different quantization schemes at different iteration numbers based on a fixed number of quantization bits. Simulation results show that the proposed adaptive quantization can reduce the number of quantization bits without error performance degradation.

In this paper, we propose to approach the capacity limit for channels with fast phase variation by using a serial concatenation scheme with an outer turbo encoder and an inner block modulator. A distinct feature of the proposed transmission scheme is that coded symbols from adjacent codewords are interleaved into the same input vectors of the block modulator. At the receiver, we not only perform the iterative noncoherent demodulation and decoding algorithm, but also exchange extrinsic information between adjacent codewords due to the codeword interleaved structure. It is shown through the extrinsic information transfer (EXIT) chart that the resultant block demodulator and channel decoder can match well with each other, and can achieve a near-capacity performance.

Partial transmit sequence (PTS) is a well-known peak-to-average power ratio (PAPR) reduction scheme based on the concept of multiple candidates. In this paper, we propose multiple-candidate separation at the receiver by turbo decoding. Both blind and semi-blind methods are proposed and applied to both the phase-rotation-based PTS scheme and cyclical-shift-based PTS scheme. The blind method in general achieves better error performance at the cost of higher complexity compared to the semi-blind method. Compared to the conventional method, both methods can provide better error performance. The proposed blind method can achieve similar error performance compared to using the perfect side information.

We investigate a binary code, which is implemented by serially concatenating a multiplexer, a multilevel delay processor, and a signal mapper to a binary turbo encoder. To achieve improved convergence behavior, we modify the binary code by passing only a fraction of the bits in the turbo code through the multilevel delay processor and the signal mapper. Two decoding methods are discussed and their performances are evaluated.

The convergence speed of layered message-passing decoding (LMPD) is faster than that of standard two phase message passing (TPMP) decoding. We propose to use dynamic scheduling and early termination to reduce computational complexity for a modified LMPD algorithm which was proposed for quasi-cyclic low-density parity-check (QC-LDPC) codes. We dynamically skip or redo the decoding operations for some layers based on appropriate criteria. An early termination strategy which is efficient in hardware implementation is also proposed in this paper. The modified MPD using these two techniques simultaneously can reduce the computational complexity with similar error performance as compared to the case of not using these two techniques.

The convergence speed of shuffled message passing decoding (MPD) is faster than that of standard two phase message passing (TPMP) decoding. Due to complex memory access and requirement of large storage space, the shuffled MPD is not suitable for hardware implementation especially for high-rate LDPC codes. In this paper, we propose a modified shuffled MPD which can achieve a similar convergence speed but with reduced complexity in memory access and storage space as compared to the conventional shuffled MPD. We implement a rate-5/6 LDPC decoder based on the proposed algorithm.

For a turbo coded BLAST (Bell LAbs Space-Time architecture) system with Nttransmit antennas and Nrreceive antennas, there is a significant gap between its detection threshold and the capacity in case Nt> Nr. In this paper, we show that by introducing a convolutional interleaver with block delay between the BLAST mapper and the turbo encoder, the threshold can be improved. Near-capacity thresholds can be achieved for some cases. To take advantage of the low detector complexity in Alamouti STBC (space-time block code), we also investigate a STBC system, which is the concatenation of the Alamouti STBC with a turbo trellis coded modulation. By using a proper labelling and adding a convolutional interleaver with block delay to such a STBC system, we achieve both lower error floors and lower thresholds.

In this paper, we modify a previously proposed decoding algorithm and propose a VLSI architecture to decode the quasi-cyclic low-density parity-check (QC-LDPC) code C used in the IEEE 802.16e standard. The modified decoding algorithm sequentially decodes a plurality of block codes for which its code length is much smaller than that of C. The proposed decoder can achieve a faster speed of convergence, lower decoding latency, higher throughput, and lower number of memory access as compared to the decoders using conventional turbo decoding message passing (TDMP) based on similar hardware complexity.

In this paper, we propose a turbo coded MIMO (multiple-input multiple-output) scheme for noncoherent fast fading channels, where neither the transmitter nor the receiver knows the channel state information. The turbo coded bits are alternatively transmitted by using the unitary space-time modulation (USTM) or spatial multiplexing (SM). At the receiver, a novel iterative detection-decoding algorithm is performed among the turbo decoder, the coherent demapper used for SM, and the noncoherent demapper for USTM. As compared to the scheme in the literature, the proposed scheme, in some cases, can provide better error performance with lower complexity.

In this paper, we propose deliberate power boost (DPB) to reduce the PAPR (peak-to-average power ratio) in an OFDM (orthogonal frequency-division multiplexing) system. Although both the average power and peak power are increased by using DPB, we show that the PAPR can be reduced by the proposed method. DPB can be combined with other PAPR-reduction techniques such as deliberate clipping and repeated clipping and filtering (RCF) for further PAPR reduction. Although selective mapping (SLM) is originally proposed for PAPR reduction, we apply a concept similar to SLM to clipping-based OFDM systems for improved error performance. We show that turbo coded OFDM systems using both RCF and DPB can achieve better PAPR performance without degrading the error performance as compared to the case of using only RCF if SLM is used for improved error performance in both systems.

In this paper, we investigate detection-decoding algorithms for the near-capacity performances of turbo coded MIMO (multiple-input multiple-output) schemes in the fast fading channel. Both the conventional turbo coded MIMO scheme Gamma0and turbo coded MIMO scheme with interblock memory which is denoted by Gamma are investigated. Gamma is implemented by introducing some delay elements between the BLAST mapper and the turbo encoder. We show that, unlike Gamma0, the extrinsic information transfer (EXIT) curves of detector and turbo decoder in Gamma can match well. Hence, Gamma can provide error performances much better than Gamma0. In particular, we find an improved detection and decoding algorithm which can closely approach the Shannon capacity.

In a turbo coded orthogonal frequency-division multiplexing (TCOFDM) system, low peak-to-average power ratio (PAPR) can be achieved by selective-mapping (SLM). In this paper, we propose to generate multiple candidates used in SLM by employing the tail-biting bits in a tail-biting turbo code. In our method, no explicit side information is needed and no error propagation is observed. Low PAPR can also be achieved by distortion-based techniques such as deliberate clipping. Although SLM is originally proposed for PAPR reduction, we also apply a concept similar to SLM to clipping-based TCOFDM systems for improved bit error rate (BER). With these proposed techniques, a tail-biting TCOFDM system can achieve both low PAPR and low BER.

In this paper, we propose a modified iterative decoding algorithm to decode a special class of quasi-cyclic low- density parity-check (QC-LDPC) codes such as QC-LDPC codes used in the IEEE 802.16e standards. The proposed decoding is implemented by serially decoding block codes with identical parity-check matrix H1derived from the parity-check matrix H of the QC-LDPC codes. The dimensions of H1are much smaller than those of H. Extrinsic values can be passed among these block codes since the code bits of these block codes are overlapped. Hence, the proposed decoding can reduce the number of iterations required by up to forty percent without error performance loss as compared to the conventional message- passing decoding algorithm. A partially-parallel very large-scale integration (VLSI) architecture is proposed to implement such a decoding algorithm. The proposed VLSI decoder can fully take advantage of the proposed decoding to increase its throughput. In addition, the proposed decoder only needs to store check-to- variable messages and hence is memory efficient.

We investigate the performance of binary codes T constructed from turbo coding with interblock memory. The encoding of T is implemented by serially concatenating a multiplexer, a multilevel delay processor, and a signal mapper to the encoder of a conventional binary turbo code C. With such a construction, in T, there is some irregularity for the code bits in C. To provide more variety of irregularity, we can construct TCwhich is obtained by passing only a fraction of C through a multilevel delay processor and a signal mapper. We propose iterative decoding between adjacent codewords (IDAC), which provides error performance much better than the iterative decoding within a single codeword (IDSC). Simulation shows that T can have a lower error floor than C for either short or long code length. In some cases, TCcan provide better error floors and waterfall regions than C.

It is known that tail-biting codes T' constructed from trellis coded modulation (TCM) with a delay processor can achieve large minimum Euclidean distances. In this paper, concatenated space-time block coding (STBC) with T' for multiple-input multiple-output (MIMO) and MIMO-OFDM (orthogonal frequency-division multiplexing) systems is investigated. We propose an improved system which is implemented by inserting a specific block interleaver between the encoders of coded modulation and STBC. We also propose sliding-window-type iterative decoding using partial hard-decision feedback (SW-IDPHF) with low complexity to decode T', which provides better error performance as compared to sliding-window-type iterative decoding using full hard-decision feedback (SW-IDFHF). In addition, we apply sliding-window-type iterative decoding using soft-decision feedback (SW-IDSF) to T' for improved error performance. The decoder of concatenated system based on T' can converge faster and provide better ultimate error performance as compared to the case of BICM under various channel conditions for either MIMO or MIMO-OFDM systems.

It is already known that a trellis code T, which is constructed by using the encoder of a convolutional code C with short constraint length followed by a delay processor and a signal mapper, is equivalent to a trellis code with large constraint length. In this paper, we derive a new lower bound on the free distance of T, which, in some cases, is better than the previously derived bound. Moreover, instead of the decoding used in earlier publications, we apply iterative decoding on both tailbiting and zero-tail representations of T to take advantage of the new lower bound and, in the meantime, to decrease the associated error coefficient caused by the decoding used in earlier publications. Comparisons among various designs of such a trellis code and some well-known coding methods are also provided.

A trellis code encoded by using the encoder of a convolutional code C with a short constraint length followed by an additional processing unit is equivalent to a trellis code with a large constraint-length. In 1993, Hellstern proposed a trellis coding scheme for which the processing unit consists of a delay processor and a signal mapper. With Hellstern's scheme, trellis codes with large free distances can be constructed. In this paper, we propose two trellis coding schemes. For the first scheme, the processing unit is composed of multiple pairs of delay processors and signal mappers. For the second scheme, the processing unit is composed of a convolutional processor and a signal mapper, where a convolutional processor is a rate 1 convolutional code. The trellis code constructed from each of the proposed schemes can be suboptimally decoded by using the trellis of the convolutional code C with some feedback information. Either of the proposed schemes can produce a trellis code that has a larger bound on free distance and better error performance as compared to the trellis code constructed from Hellstern's scheme based on the same convolutional code C.