A capacitive cross-coupled common drain amplifier for audio applications is presented with 65.5 dBA SNR, 425 µW power consumption and an output sensitivity at 1 Pa pressure of -39 dBV. Capacitive cross-coupling can reduce the output voltage to -43 dBV. A CMFB is used for DC bias over the microphone. The sensor used is a stage-based piezoelectric MEMS microphone.

The challenge for trapped ion quantum computers (TIQC) is scaling the system with its large number of IOs. Analog multiplexers operated near the trap are essential to enable large-scale TIQC. This paper presents an analog switch that can be used as a building block for the required analog multiplexers. The switching cell operates down to a temperature of 4 K. It can block an input voltage of 20 V (±10 V). At 77 K, the switch has an on-resistance of around 300 Ω. It consumes 39 µW in the closed state and 19.5 µW in the open state. Although the switch operates down to 4 K, the carrier freeze-out in the drift region causes non-linearity in the switch’s on-resistance.

The project VE-FIDES will contribute with a solution based on an innovative multi-level fingerprinting approach to secure electronics supply chains against the threats of malicious modification, piracy, and counterfeiting. Hardware-fingerprints are derived from minuscule, unavoidable process variations using the technology of Physical Unclonable Functions (PUFs). The derived fingerprints are processed to a system fingerprint enabling unique identification, not only of single components but also on PCB level. With the proposed concept, we show how the system fingerprint can enhance the trustworthiness of the overall system. For this purpose, the complete system including tiny sensors, a Secure Element and its interface to the application is considered in VE-FIDES. New insights into methodologies to derive component and system fingerprints are gained. These techniques for the verification of system integrity are complemented by methods for preventing reverse engineering. Two application scenarios are in the focus of VE-FIDES: Industrial control systems and an automotive use case are considered, giving insights to a wide spectrum of requirements for products built from components provided by international supply chains.

This paper proposes a new fully CMOS-compatible PUF primitive robust against process variations, supply voltage variations and temperature drift (PVT) based on resistive structures that implements advanced compensation mechanisms already on circuit level. Based on analog simulation data, the PUF is evaluated regarding its unpredictability and its reliability. The results indicate a high quality. Further, a structured approach for designing a suitable error correction is presented to illustrate the whole PUF system.

Compute-In-Memory (CIM) enables accelerating multiply-accumulate computations (MACs) by non von Neumann architecture analog crossbars. However, computation precision and power efficiency suffer from parasitic wire resistance and power-consuming data-converters with conventional voltage-mode crossbar. Increasing crossbar size to further enhance computation/power efficiency can only be achieved on the premise that those problems can be solved. This work proposes a charge-transfer-based crossbar, where the accumulation is performed by counting the transferred charges into capacitors. Thanks to the time-discrete property of the charge transfer and adaptive body-biasing (ABB) current generator, the entire proposed crossbar is almost fully dynamic and very insensitive to parasitic wire resistance without DAC/ADC needed. In addition, adaptive reference technique is applied to realize a self-adjustable operating range for quantitated neural network computations. The proposed crossbar prototype is designed with 22nm-FDSOI and post-simulated with a size of $128 \times 128$. A computation and power efficiency of 1024GOP/s and 78TOPS/w is achieved for computation with 4-bit inputs, 1-bit weight, and 4-bit output. Both computation-and power efficiency can be further enhanced by enlarging the crossbars’ size without any significant loss of the computation precision.

The field of computer hardware stands at the verge of a revolution driven by recent breakthroughs in emerging nanodevices. “Nano Security” is a new Priority Program recently approved by DFG, the German Research Council. This initial-stage project initiative at the crossroads of nano-electronics and hardware-oriented security includes 11 projects with a total of 23 Principal Investigators from 18 German institutions. It considers the interplay between security and nano-electronics, focusing on a dichotomy which emerging nano-devices (and their architectural implications) have on system security. The projects within the Priority Program consider both: potential security threats and vulnerabilities stemming from novel nano-electronics, and innovative approaches to establishing and improving system security based on nano-electronics. This paper provides an overview of the Priority Program's overall philosophy and discusses the scientific objectives of its individual projects.

The size of crossbar-like resistive multiplication accumulation (MAC) accelerators is restricted by parasitic interconnect resistances limiting the computation efficiency. In order to understand the impact of the interconnect (wire) resistance on the computation accuracy, this work proposes a modelling methodology for adapting the neural network weights regarding the weight error caused by wire resistance. Even more, this work investigates the maximal achievable crossbar size based on the proposed design variable "the minimal allowed weight error ratio Ron/Reqv" instead of using an iterative numerical method. Using the proposed method this work investigate the computation accuracy improvement through splitting the layer computation into multiple small crossbars. The result indicates that simply separating the computation into multiple small crossbar does not improve the accuracy always. Considering the minimal Ron/Reqv can more easily result in a proper crossbar size.

A holistic power saving concept for ultra-low-power microcontroller (MCU) systems involving application requirements, system architecture, and circuit design techniques is presented. The key of this concept is a digitally enhanced low dropout regulator (LDO) supplying the MCU digital core. By making use of known system power information, the LDO digitally adapts its maximum current drive capability up to 2.56 mA while its quiescent current is as low as 650 nA in light load conditions. In this way, the power management overhead is drastically reduced when operating at low clock speeds enabling system energy savings of 31% at 1 MHz. At the same time, a drastic reduction of the LDO output capacitance enables ultra-low-power consumption during sleep and energy efficient wake-up, resulting in system energy savings up to a factor of 4.6.

Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub- 100nm technologies. In this work we investigate the variability of flip flop race immunity in 130nm and 90nm low power CMOS technologies. An on-chip measurement technique with resolution of ˜1ps is used to characterize hold time violations of flip flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Statistical die-to die variations of hold time violations are measured various register-to-register configurations and show overall 3σ die-to-die standard deviations of 12–16% Mathematical methods to separate the measured variability between systematic and random variability are discussed, and the results presented. They show that while systematic variability is the major issue in 130nm, it is significantly decreased in 90nm technology due to better process control. Another important point is that the race immunity decreases about 30% in 90nm, showing that smaller clock skews can lead to violations in 90nm.

CMOS-based sensor array chips provide new and attractive features as compared to today's standard tools for medical, diagnostic, and biotechnical applications. Examples for molecule- and cell-based approaches and related circuit design issues are discussed.