Since its inception, the semiconductor industry has used a physical dimension (the minimum gate length of a transistor) as a means to gauge continuous technology advancement. This metric is all but obsolete today. As a replacement, we propose a density metric, which aims to capture how advances in semiconductor device technologies enable system-level benefits. The proposed metric can be used to gauge advances in future generations of semi-conductor technologies in a holistic way, by accounting for the progress in logic, memory, and packaging/integration technologies simultaneously.

This month’s issue offers insight into efficient compression and execution of DNNs, the challenge of connecting rural areas, and the clique problem in wireless communication. which

In this paper, we propose a novel MOSFET parameter extraction method to enable early technology evaluation. The distinguishing feature of the proposed method is that it enables the extraction of MOSFET model parameters using limited and incomplete current–voltage measurements from on-chip monitor circuits. An important step in this method is the use of maximuma posterioriestimation where past measurements of transistors from various technologies are used to learn a prior distribution and its uncertainty matrix for the parameters of the target technology. The framework then utilizes Bayesian inference to facilitate extraction using a very small set of additional measurements. The proposed method is validated using various past technologies and post-silicon measurements for a commercial 28-nm process. The proposed extraction can be used to characterize the statistical variations of MOSFETs with the significant benefit that the restrictions imposed by the backward propagation of variance algorithm are relaxed. We also study the lower bound requirement for the number of transistor measurements needed to extract a full set of parameters for a compact model. Finally, we propose an efficient algorithm for selecting the optimal transistor biases by minimizing a cost function derived from information-theoretic concept of average marginal information gain.

In this paper, we propose a novel MOSFET parameter extraction method to enable early technology evaluation. The distinguishing feature of the proposed method is that it enables the extraction of an entire set of MOSFET model parameters using limited and incomplete IV measurements from on-chip monitor circuits. An important step in this method is the use of maximum-a-posteriori estimation where past measurements of transistors from various technologies are used to learn a prior distribution and its uncertainty matrix for the parameters of the target technology. The framework then utilizes Bayesian inference to facilitate extraction using a very small set of additional measurements. The proposed method is validated using various past technologies and post-silicon measurements for a commercial 28-nm process. The proposed extraction could also be used to characterize the statistical variations of MOSFETs with the significant benefit that some constraints required by the backward propagation of variance (BPV) method are relaxed.

In this paper, we propose a novel integrated circuits performance estimation algorithm through a physical subspace projection and maximum-a-posteriori (MAP) estimation. Our goal is to estimate the distribution of a target circuit performance with very small measurement sample size from on-chip monitor circuits. The key idea in this work is to exploit the fact that simulation and measurement data are physically correlated under different circuit configurations and topologies. First, different groups of measurements are projected to a subspace spanned by a set of physical variables. The projection is achieved by performing a sensitivity analysis of measurement parameters with respect to the subspace variables using a virtual source MOSFET compact model. Then a Bayesian treatment is developed by introducing prior distributions over these subspace variables. Maximum a posteriori estimation is then applied using the prior, and an expectation-maximization (EM) algorithm is used to estimate the circuit performance. The proposed method is validated by postsilicon measurement for a commercial 28-nm process. An average error reduction of 2x is achieved which can be translated to 32x reduction on data size needed for samples on the same die. A 150x and 70x sample size reduction on training dies is also achieved compared to traditional least-square fitting method and least-angle regression method, respectively, without reducing accuracy.

In this paper, we present the first validation of the virtual source (VS) charge-based compact model for standard cell libraries and large-scale digital circuits. With only a modest number of physically meaningful parameters, the VS model accounts for the main short-channel effects in nanometer technologies. Using a novel DC and transient parameter extraction methodology, the model is verified with simulated data from a well-characterized, industrial 40-nm bulk silicon model. The VS model is used to fully characterize a standard cell library with timing comparisons showing less than 2.7% error with respect to the industrial design kit. Furthermore, a 1001-stage inverter chain and a 32-bit ripple-carry adder are employed as test cases in a vendor CAD environment to validate the use of the VS model for large-scale digital circuit applications. Parametric Vdd sweeps show that the VS model is also ready for usage in low-power design methodologies. Finally, runtime comparisons have shown that the use of the VS model results in a speedup of about 7.6×.

A statistical extension of the ultra-compact Virtual Source (VS) MOSFET model is developed here for the first time. The characterization uses a statistical extraction technique based on the backward propagation of variance (BPV) with variability parameters derived directly from the nominal VS model. The resulting statistical VS model is extensively validated using Monte Carlo simulations, and the statistical distributions of several figures of merit for logic and memory cells are compared with those of a BSIM model from a 40-nm CMOS industrial design kit. The comparisons show almost identical distributions with distinct run time advantages for the statistical VS model. Additional simulations show that the statistical VS model accurately captures non-Gaussian features that are important for low-power designs.

Recent advances in nanophotonic device research have led to a proliferation of proposals for new architectures that employ optics for on-chip communication. However, since standard simulation tools have not yet caught up with these advances, the quality and thoroughness of the evaluations of these architectures have varied widely. This paper provides the first complete end-to-end analysis of an architecture using on-chip optical interconnect. This analysis incorporates realistic performance and energy models for both electrical and optical devices and circuits into a full-fledged functional simulator, thus enabling detailed analyses when running actual applications. Since on-chip optics is not yet mature and unlikely to see widespread use for several more years, we perform our analysis on a future 1000-core processor implemented in an 11nm technology node. We find that the proposed optical interconnect can provide between 1.8x and 4.8x better energy-delay product than conventional electrical-only interconnects. In addition, based on a detailed energy breakdown of all processor components, we conclude that a thermal ring resonators and on-chip lasers that allow rapid power gating are key areas worthy of additional nanophotonic research. This will help guide future optical device research to the areas likely to provide the best payoff.

Summary form only given. Leading edge CMOS technologies today are unique examples of nanoscale engineering at an industrial scale. As we celebrate this remarkable achievement of our industry that forms the ever-expanding technology basis of modern society we cannot help but ponder the question of how we can continue to push the envelope of nano-electronics. With the end of Si FET scaling appearing increasingly near, searching for more scalable transistor structures in Si and in ¿beyond-Si¿ solutions has become imperative; from relatively ¿easy¿ transitions to non-planar Si structures, to the incorporation of high mobility semiconductors, like Ge and III-V's, to even higher mobility new materials such as carbon nanotubes, graphene, or other molecular structures. And even further, there are searches for new information representation and processing concepts beyond charge in FETs, as for example, in spin-state devices. Of course, declaring silicon dead is premature at best, and with this in mind I will discuss the challenges and possible scenaria for the introduction of novel nano-electronic devices.

The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, control switching power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. With threshold voltage scaling sub-threshold leakage power is expected to become a significant portion of the total power in future CMOS systems. Therefore, it becomes crucial to predict sub-threshold leakage power of such systems. In this paper, we present a sub-threshold leakage power prediction model that takes into account within-die threshold voltage variation. Statistical measurements of 32-bit microprocessors in 0.18 mm CMOS confirms that the mean error of the model to be 4%. Comparisons of this model to two other existing models that do not take within-die threshold voltage variation into account are also presented.

Article Share on Scaling of stack effect and its application for leakage reduction Authors: Siva Narendra Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA and Microprocessor Research Laboratories, Intel Corporation, Hillsboro, OR Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA and Microprocessor Research Laboratories, Intel Corporation, Hillsboro, ORView Profile , Vivek De Microprocessor Research Laboratories, Intel Corporation, Hillsboro, OR Microprocessor Research Laboratories, Intel Corporation, Hillsboro, ORView Profile , Dimitri Antoniadis Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MAView Profile , Anantha Chandrakasan Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MAView Profile , Shekhar Borkar Microprocessor Research Laboratories, Intel Corporation, Hillsboro, OR Microprocessor Research Laboratories, Intel Corporation, Hillsboro, ORView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 195–200https://doi.org/10.1145/383082.383132Online:06 August 2001Publication History 140citation1,436DownloadsMetricsTotal Citations140Total Downloads1,436Last 12 Months24Last 6 weeks3 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. However, no methodologies have been developed to size the high V t sleep transistor in an intelligent manner that trades off area and performance. In fact, many attempts at sizing the sleep transistor without close consideration of input vector patterns or internal structures can lead to large overestimates or large underestimates in sleep transistor sizing. This paper describes some of the issues involved in sizing transistors for MTCMOS and also introduces a variable breakpoint switch level simulator that can rapidly calculate delay in MTCMOS circuits as functions of design variables such as V dd , V t , and sleep transistor sizing. 1. BACKGROUND Power consumption in conventional CMOS circuits can be attributed to switching power, leakage power, and short circuit power. Switching power is usually the dominant term and is given by the well known formula: P switchi...

This paper provides an overview of SO1 MOSFRT theory and practice with emphasis on circuit applications issues.Fully and partially depleted channel devices are considered and particular attention is given to describing the so-called floating-body effects that are unique to SOL Two advanced SO1 MOSFHT configurations, dual-gate SO1 and activebody SOI, specifically developed for low voltage circuit applications are also discussed.Permission to make digital/hard copy of all or part of this work for personal or dassmom use is granted without fee provided that copies are not made or distributed

Aggressive voltage scaling to 1V and below through technology, circuit, and architecture optimization has been proven to be the key to ultra low-power design.The key technology trends for low-voltage operation are presented including low-threshold devices, multiple-threshold devices, and SOI and bulk CMOS based variable threshold devices.The requirements on CAD tools that allow designers to choose and optimize various technology, circuit, and system parameters are also discussed.

This paper describes a Galerkin/spherical harmonics approach for solving the coupled Poisson-Boltzmann system of equations for the electron distribution function and the electric potential, which can then be used to calculate other parameters of interest such as current flow and electron temperature. The Galerkin approach described here has some pragmatic advantages in space-dependent problems over more commonly used term-matching techniques for arbitrary order spherical harmonic expansions in momentum space, but the method requires a careful treatment of the boundary conditions and upwinded discretization methods. Results are presented for nonuniformly doped one-dimensional devices using up to third order spherical harmonics to show the importance of including higher order harmonics to accurately calculate the distribution function in high field regions.

The authors develop a robust and efficient numerical solution of the hydrodynamic model, which solves the energy balance equation, and compare predictions of this model, using one set of parameters, with experimental nMOSFET characteristics for a range of channel lengths down to ultrashort channels. The substrate current is calculated by direct integration of the energy distribution function, which uses the computed temperature to obtain the number of high energy electrons. The drain current calculated using this method is accurate for a range of channel lengths and biases, and correctly predicts the observed enhanced transconductance for ultrashort-channel devices. The substrate current matches the experimental data for a range of channel lengths and biases above threshold with one set of physically reasonable parameters.>

Quantum effects resulting from sub-100 nm features in planar, field-effect-controlled semiconductor structures or devices are discussed, and experimental results are compared with calculations. These devices are based on the GaAs-AlGaAs modulation-doped field-effect transistor (MODFET) and include grating-gate lateral surface superlattices. (LSSLs), grid-gate LSSLs, planar-resonant-tunneling field-effect transistors (PRESTFETs), multiple parallel quantum wires (MPQWs), and arrays of quantum dots (QDs). In contrast to conventional, epitaxially grown vertical quantum structures, planar structures offer the opportunity for electron confinement in three, two, and one dimensions and the flexibility of electrical tuning of quantum effects.>

At temperatures encountered in thermal oxidation, silicon dioxide flows viscoelastically, A reduced-dimension, generalized boundary element method for modeling such a problem has been developed. A modified Kelvin's solution is used as the kernel; constant-velocity loading is chosen to operate with a wide range of stress relaxation times. Simulation results are reported for simple cases of focal oxidation.>

Thermal oxidation of silicon involves the diffusion of oxidant molecules from the gas-oxide interface to the oxide-silicon interface, and the transport of newly formed oxide away from the latter. Under suitable formulations these two processes can be shown to be boundary-value problems of harmonic and biharmonic nature. Based on these properties, a boundary integral equation method (BIEM) has been developed for modeling oxidation. This method achieves simplicity and efficiency by solving a two-dimensional problem using line integrals on the boundaries. The use of source distributions as intermediary solutions facilitates direct calculations of a wide variety of boundary parameters.