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Stephan Tobies

dblp:26/6947 · DBLP profile ↗
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13ranked-venue papers
3as first author
0since 2021 · last 2020
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Theory of computation · 9 · 2 first-authorArtificial intelligence and machine learning · 6 · 2 first-authorSoftware engineering, systems software and programming languages · 5Systems, architecture and hardware · 2Computer networks · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
2 papers
Program verification · 100%
Theoretical computer science
1 paper
Automated reasoning and model checking · 100%
Artificial intelligence
1 paper
Knowledge representation and reasoning · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Program verification
concurrent program verification
0.112010
Local Verification of Global Invariants in Concurrent Programs · CAV 2010
Automated reasoning and model checking › program verification
program invariants
0.112010
Local Verification of Global Invariants in Concurrent Programs · CAV 2010
Knowledge, reasoning and agents › Knowledge representation and reasoning
automated reasoning
0.012000
Reasoning with Axioms: Theory and Practice · KR 2000
Knowledge, reasoning and agents › Knowledge representation and reasoning
description logic
0.012000
Reasoning with Axioms: Theory and Practice · KR 2000

Methods — techniques the papers use, named apart from their topics

rely-guarantee reasoning · 0.2compositional verification · 0.2axiom pinpointing · 0.0
YearPublicationVenuePosition
2020 ARM-on-ARM: Leveraging Virtualization Extensions for Fast Virtual Platforms
abstract
Virtual Platforms (VPs) are an essential enabling technology in the System-on-a-Chip (SoC) development cycle. They are used for early software development and hardware/soft- ware codesign. However, since virtual prototyping is limited by simulation performance, improving the simulation speed of VPs has been an active research topic for years. Different strategies have been proposed, such as fast instruction set simulation using Dynamic Binary Translation (DBT). But even fast simulators do not reach native execution speed. They do however allow executing rich Operating System (OS) kernels, which is typically infeasible when another OS is already running.Executing multiple OSs on shared physical hardware is typically accomplished by using virtualization, which has a long history on x86 hardware. It enables encapsulated, native code execution on the host processor and has been extensively used in data centers, where many users share hardware resources. When it comes to embedded systems, virtualization has been made available recently. For ARM processors, virtualization was introduced with the ARM Virtualization Extensions for the ARMv7 architecture. Since virtualization allows native guest code execution, near-native execution speeds can be reached.In this work we present a VP containing a novel ARMv8 SystemC Transaction Level Modeling 2.0 (TLM) compatible processor model. The model leverages the ARM Virtualization Extensions (VE) via the Linux Kernel-based Virtual Machine (KVM) to execute the target software natively on an ARMv8 host. To enable the integration of the processor model into a loosely-timed VP, we developed an accurate instruction counting mechanism using the ARM Performance Monitors Extension (PMU). The requirements for integrating the processor model into a VP and the integration process are detailed in this work.Our evaluations show that speedups of up to 2.57x over state-of-the-art DBT-based simulator can be achieved using our processor model on ARMv8 hardware.
Lukas Jünger 0001, Jan Luca Malte Bölke, Stephan Tobies, Rainer Leupers, Andreas Hoffmann 0002
DATE3
2018 OHEX: OS-aware hybridization techniques for accelerating MPSoC full-system simulation
abstract
Virtual platform (VP) technology is an established enabler of embedded system design. However, the sheer number of CPU models in modern multi-core VPs forms a performance bottleneck. Hybrid simulation addresses this issue by executing parts of the embedded software stack on the host. Although the approach is significantly faster, hybridization can not cope with higher software layers, e.g., Operating Systems (OSs). Thus, this paper presents the OS-aware Host EXtension (OHEX) framework to accelerate VPs while expanding the applicability of hybridization. OHEX is evaluated on various system layers, yielding speedups between 2.99x-21.14x with specific benchmarks.
Robert Buecs, Maximilian Fricke, Rainer Leupers, Gerd Ascheid, Stephan Tobies, Andreas Hoffmann 0002
DATE5
2011 The 1st Verified Software Competition: Experience Report
Vladimir Klebanov, Peter Müller 0001, Natarajan Shankar, Gary T. Leavens, Valentin Wüstholz, Eyad Alkassar, Rob Arthan, Derek Bronish, Roderick Chapman, Ernie Cohen, Mark A. Hillebrand, Bart Jacobs 0002, K. Rustan M. Leino, Rosemary Monahan, Frank Piessens, Nadia Polikarpova, Tom Ridge, Jan Smans, Stephan Tobies, Thomas Tuerk, Mattias Ulbrich, Benjamin Weiß 0001
FM19
2010 Local Verification of Global Invariants in Concurrent Programs
Ernie Cohen, Michal Moskal, Wolfram Schulte, Stephan Tobies
CAV4
2002 Formal Test Purposes and the Validity of Test Cases
Peter H. Deussen, Stephan Tobies
FORTE2
2001 PSPACE Reasoning for Graded Modal Logics
abstract
We present a PSpace algorithm that decides satisfiability of the graded modal logic Gr(KR) - a natural extension of propositional modal logic KR by counting expressions - which plays an important role in the area of knowledge representation. The algorithm employs a tableaux approach and is the rst known algorithm which meets the lower bound for the complexity of the problem. Thus, we exactly fix the complexity of the problem and refute an ExpTime-hardness conjecture. We extend the results to the logic Gr(K R 1 \\ ), which augments Gr(KR) with inverse modalities and intersection of accessibility relations. This establishes a kind of "theoretical benchmark" that all algorithmic approaches can be measured with.
Stephan Tobies
J. Log. Comput.1
2000 A Tableau Algorithm for the Clique Guarded Fragment
abstract
this paper, we generalise the principles from tableau algorithms for modal logics in order to develop a tableau algorithm for CGF. To the best of our knowledge, this is the rst algorithm for CGF that can be used as the basis for an ecient implementation
Colin Hirsch, Stephan Tobies
Advances in Modal Logic2
2000 Reasoning with Individuals for the Description Logic SHIQ
Ian Horrocks 0001, Ulrike Sattler, Stephan Tobies
CADE3
2000 Reasoning with Axioms: Theory and Practice
Ian Horrocks 0001, Stephan Tobies
KR2
2000 How to Decide Query Containment Under Constraints Using a Description Logic
Ian Horrocks 0001, Ulrike Sattler, Sergio Tessaris, Stephan Tobies
LPAR4
2000 The Complexity of Reasoning with Cardinality Restrictions and Nominals in Expressive Description Logics
abstract
We study the complexity of the combination of the Description Logics ALCQ and ALCQI with a terminological formalism based on cardinality restrictions on concepts. These combinations can naturally be embedded into C^2, the two variable fragment of predicate logic with counting quantifiers, which yields decidability in NExpTime. We show that this approach leads to an optimal solution for ALCQI, as ALCQI with cardinality restrictions has the same complexity as C^2 (NExpTime-complete). In contrast, we show that for ALCQ, the problem can be solved in ExpTime. This result is obtained by a reduction of reasoning with cardinality restrictions to reasoning with the (in general weaker) terminological formalism of general axioms for ALCQ extended with nominals. Using the same reduction, we show that, for the extension of ALCQI with nominals, reasoning with general axioms is a NExpTime-complete problem. Finally, we sharpen this result and show that pure concept satisfiability for ALCQI with nominals is NExpTime-complete. Without nominals, this problem is known to be PSpace-complete.
Stephan Tobies
J. Artif. Intell. Res.1
1999 A PSpace Algorithm for Graded Modal Logic
Stephan Tobies
CADE1
1999 Practical Reasoning for Expressive Description Logics
Ian Horrocks 0001, Ulrike Sattler, Stephan Tobies
LPAR3