EDBT 2026 Demo / reviewers in the wild / expert
Eylon Caspi
dblp:26/7014
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2002
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Reconfigurable computing and FPGAs · 33% Electronic design automation · 33% Parallel and multicore computing · 33% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing › dataflow computing › dataflow scheduling
quasi-static scheduling |
0.0 | 1 | 2002 | Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine · FPGA 2002 |
Reconfigurable computing and FPGAs
reconfigurable computing |
0.0 | 1 | 2002 | Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine · FPGA 2002 |
Electronic design automation › high-level synthesis
scheduling |
0.0 | 1 | 2002 | Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine · FPGA 2002 |
Compilers and program optimization › instruction scheduling
compile-time scheduling |
0.0 | 1 | 2002 | Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine · FPGA 2002 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2002 | Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machineabstractThe SCORE compute model uses fixed-size, virtual compute and memory pages connected by stream links to capture the definition ofa computation abstracted from the detailed size ofthe physical hardware. When the number of physical compute pages is smaller than the number of virtual compute pages in the abstract computation graph, the design is time-multiplexed onto the available physical hardware. A key component ofthis strategy is an automatic scheduler that selects the temporal sequencing ofvirtual resources onto the physical device. We describe a quasistatic scheduling strategy that retains the full semantic power of the dynamic SCORE flow graph while taking advantage ofstatic scheduling techniques at program load time to hoist most ofthe computational work out of the inner scheduling loops. This strategy reduces online scheduling work per reconfiguration epoch by an order of magnitude. In addition, a more global perspective available from offline-scheduling improves schedule quality, resulting in a net reduction oftotal execution time by 46–81%. 1. Yury Markovsky, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, André DeHon |
FPGA | 2 |