Abstract Cloud adoption has significantly increased using the infrastructure-as-a-service (IaaS) paradigm, in order to meet the growing demands of computing, storage and networking, in small as well as large enterprises. Different vendors provide their customized solutions for OpenStack deployment on bare metal or virtual infrastructure. Among these many available IaaS solutions, OpenStack stands out as being an agile and open-source platform. However, its deployment procedure is a time-taking and complex process with a learning curve. This paper addresses the lack of basic infrastructure automation in almost all of the OpenStack deployment projects. We propose a flexible framework to automate the process of infrastructure bring up for deployment of several OpenStack distributions, as well as resolving dependencies for a successful deployment. Our experimental results demonstrate the effectiveness of the proposed framework in terms of automation status and deployment time, that is, reducing the time spent in preparing a basic virtual infrastructure by four times, on average.

Parallel discrete event simulation frameworks have been widely used to analyze the performance of traditional applications under different scenarios. The existing frameworks are designed to work on a cluster and cloud-based computing environments. With the current advances in the Internet of Things, there is a strong need to revamp such traditional frameworks and make use of the smart connected-devices as an underlying infrastructure to perform simulations. In this article, we propose a new simulation framework, which has been specifically designed to work with diverse heterogeneous devices. The framework allows these heterogeneous mobile devices to participate in a distributed simulation while managing network latency, using device profiles that are maintained by the simulation framework. Moreover, in the proposed framework, random and context-aware simulation task distributions have been explored to manage the devices’ sporadic connectivity. Evaluation results using the well-known PHOLD benchmark demonstrate a gain in the overall efficiency of the proposed simulation system.

We introduce a static binary translation flow in native simulation context for cross-compiled VLIW executables. This approach is interesting in situations where either the source code is not available or the target platform is not supported by any retargetable compilation framework, which is usually the case for VLIW processors. The generated simulators execute on a Hardware-Assisted Virtualization (HAV) based native platform. We have implemented this approach for a TI C6x series processor and our simulation results show a speed-up of around two orders of magnitude compared to the cycle accurate simulators.

Integration of multiple heterogeneous processors into a single system-on-a-chip is a clear trend in embedded devices. Designing and verifying these devices requires high-speed and easy-to-build simulation platforms. Among the software simulation approaches, native simulation is a good candidate since the embedded software is executed natively on the host machine, and no instruction set simulator development effort is necessary. However, existing native simulation approaches are such that the simulated software shares the memory space of the modeled hardware modules and the host operating system, making impractical the support of legacy code running on the target platform. To overcome this issue seldom mentioned in the literature, we propose the addition of a transparent address space translation layer to separate the target address space from the host simulator one. For this, we exploit the hardware-assisted virtualization technology now available on most general-purpose processors. Experiments show that this solution does not degrade the native simulation speed, while keeping the ability to accomplish software performance evaluation.