Hybrid Optical Network-on-Chip (HONoC) recently emerged as a compelling solution for handling future communication needs in the many-core System-on-Chip (SoC). However, designing a HONoC poses a number of challenges that do not exist in the electronic realm, particularly crosstalk noise, which affects signal-to-noise ratios (SNR). As a result, it affects network scalability and power consumption. In this paper, we have used the Kernighan-Lin (KL) based application mapping technique to optimize the SNR. We have compared our proposed method with State-of-the-art (SOTA) methods, including the Reinforcement Learning (RL) based technique. Experimental results indicate improved performance compared to SOTA methods, in terms of maximizing SNR and throughput, highlighting the potential of our approach to enhance the efficiency of these synthesized network architectures.

Hybrid optical networks-on-chip (HONoCs) can deal with future communication needs in many-core Systems-on-Chip (SoCs) designs due to their ultrahigh bandwidth, low energy consumption, routing capability and arbitration scalability. However, crosstalk noise in the HONoCs is a roadblock, which affects the signal-to-noise ratio (SNR), thus limiting the network scalability and resulting in a non-functional architecture. To prevent such a significant obstacle, application mapping techniques could be an effective approach. We have presented a meta-heuristic application mapping technique to maximize the SNR by reducing the crosstalk noise in this work. The experimental results indicate that our proposed approach can significantly reduce the crosstalk noise and increase the throughput compared to the State-of-the-art (SOTA) method which can enhance the system’s scalability.

In the evolving landscape of many-core architectures, the Network on Chip (NoC) emerges as a pivotal inter-connection framework, accommodating the escalating number of cores on a single chip. Despite its widespread adoption, power consumption remains a critical challenge, significantly influenced by factors such as topology, bit toggling, and routing algorithms, with bit-switching power being a predominant concern. In this work, we have proposed an innovative technique in the cores aimed at reducing the power consumption of the NoC. To calculate our method's area, time, and power consumption, we have synthesized it on a Xilinx Virtex-7 FPGA board. We have modified the Noxim open-source simulator to validate our approach using synthetic traffic. Empirical results demonstrate a 29.64% reduction in dynamic power consumption and a 29.09% improvement in switching activity for the average case (Mode 1) traffic scenario.

3D Network-on-Chip (NoC) technology has emerged as a compelling solution in modern System-on-Chip (SoC) designs. This NoC technology effectively addresses the escalating need for high-performance and energy-efficient on-chip communication in various applications, including High-Performance Computing (HPC), Graphics Processing Units (GPUs), and Multi-Processor SoCs (MPSoCs). However, the efficient mapping of applications onto 3D NoCs remains a complex challenge, necessitating the development of improved algorithms to address the issue. In this context, we present a novel neural mapping model with a reinforcement learning (RL) approach (NeurMap3D) to design application-specific 3D NoC-based IC. Additionally, we propose the NCTPAM (neural congestion-aware Through-Silicon Vias (TSVs) placement and application mapping) approach, which not only addresses application mapping but also incorporates TSVs placement and load balance across the TSVs for the specific application. In order to reduce the CPU execution time of NCTPAM algorithm, we propose incorporating a partial model parameter (θ) update mechanism. Experimental results indicate improved performance in terms of minimizing communication cost, load balancing across TSVs and energy consumption, highlighting the potential of our approach to enhance the efficiency of these synthesized network architectures.

Finding an optimal application mapping solution in a manycore processor is an NP-hard problem. Heuristic search techniques have the advantage of finding near-optimal solutions faster than other methods when mapping large-scale applications. However, the majority of the heuristic-based application mapping methods easily fall into local minima. Machine learning (ML) methods can learn heuristics from training data on their own, require minimal assistance from humans, and produce better mapping solutions. Recently, a reinforcement learning-based framework (RLF) has been proposed to generate the initial population for metaheuristics, designed using genetic algorithm (GA) and particle swarm optimization (PSO). The RLF framework does not incorporate reward information while generating mapping solutions. However, the model performance can be improved further by refining the network parameters using the reward information during predictions. To overcome this challenge, we propose an active search framework (ASF). For the first time, we propose a new intellectual property (IP)-core numbering scheme, which will assist ASF in learning the mapping rules more effectively. We demonstrate that REINFORCE with multiple samples (predictions) per data point improves model accuracy and reduces variance by constructing a baseline using these samples. With these, we propose two RL models: active search (ATSR) and active search with pretraining (ATSRP). According to experimental results, both ATSRP and ATSR models produce better mapping solutions compared to RLF and other state-of-the-art methods. The results suggest that the ATSRP model is better suited for performing application mapping onto a 2-D mesh-based manycore processor. Finally, we extend this framework to other performance metrics and 3-D mesh-based manycore processors.

Rapid progress in technology scaling has introduced massive parallel computing systems with multiple cores on the integrated circuit (IC), in which a flexible and scalable packet-switched architecture, Network-on-Chip (NoC), is commonly used for communication among the cores. However, technology scaling has also increased the susceptibility to internal defects in such systems. So, manufacturing tests of such multicore systems is crucial and this is a complex and time-consuming process. Due to stress on time-to-market, test engineers focus on the reduction of testtime and perform parallel tests of cores. Due to aggressive technology scaling into the nanometer regime, power consumption is also becoming a significant burden. Moreover, power consumption during manufacturing tests is more as compared to normal operation. In addition, peak power consumption is often significantly higher than the average power values. The consumed power leads to high temperature and creates hotspots, which in turn leads to failure of good parts, resulting in yield loss. Thermal safety during testing is an utmost challenging problem in NoC-based multicore systems, including three-dimensional NoC-based (3D NoC) multicore systems due to stacking of layers. This work proposes a preemptive test scheduling technique for NoC-based multicore systems to reduce the testtime by minimizing conflicts of resource usage. The preemptive test scheduling problem has been formulated using Integer Linear Programming (ILP). In this article, authors have also presented a thermal-aware test scheduling technique to test cores in 2D as well as 3D stacked NoC-based multicore systems using a Particle Swarm Optimization (PSO) based approach. To improve the solution further, several innovative augmentation techniques have been incorporated in the basic PSO. Experimental results highlight the effectiveness of the proposed method in reducing testtime and peak temperature under the power constraints and achieve a tradeoff between testtime and peak temperature.

Rapid progress in technology scaling makes transistors smaller and faster over successive generations, and consequently core count in a system gets increased. However, transistor power consumption no longer scales commensurately. Increased power density calls for better thermal safety of the multi-core systems, in which a flexible and scalable packet-switched architecture - Network-on-Chip (NoC) - is commonly used for communication among the cores. This paper proposes a strategy to increase the thermal safety of NoC-based systems by a graceful decrease in communication cost and an Integer Linear Programming (ILP) formulation to deal with the problem. To overcome huge computational overhead of ILP, another solution strategy, based on meta-heuristic technique, Particle Swarm Optimization (PSO) is also proposed. Several innovative augmentations have been introduced into the basic PSO to generate better quality solutions. A thermal-aware mapping heuristic is proposed to generate some intelligent solutions, which become a part of the initial population in the PSO. A trade-off has been established between communication cost and peak temperature of the die. Experiments on Big data and Graph analytical workloads are reported. The results obtained are better than those of many contemporary approaches, reported in the literature.

This brief proposes an on-line transparent test technique for detection of latent hard faults which develop in first-input first-output buffers of routers during field operation of NoC. The technique involves repeating tests periodically to prevent accumulation of faults. A prototype implementation of the proposed test algorithm has been integrated into the router-channel interface and on-line test has been performed with synthetic self-similar data traffic. The performance of the NoC after addition of the test circuit has been investigated in terms of throughput while the area overhead has been studied by synthesizing the test hardware. In addition, an on-line test technique for the routing logic has been proposed which considers utilizing the header flits of the data traffic movement in transporting the test patterns.

This paper presents a fault tolerant reconfigurable Network-on-Chip (NoC) architecture using router redundancy. In case of occurrence of fault in the active router, the spare router takes its place thus the system operates normally. This scheme is topology independent, so any topology with defined routing algorithm is suitable for implementation. The system has been compared in terms of reliability, mean time to failure (MTTF) and area overhead with existing works. For a 10 × 10 mesh, it gives a 1.14 reliability gain over quad-spare mesh, 1.42 reliability gain over column-spare mesh and 21.195 reliability gain over normal mesh. The mean time to failure (MTTF) gains over column-spare, quad spare and normal mesh are 3.19, 7.51, and 33.38 respectively. We have also presented a system performance report which includes throughput and latency of the proposed design.

This paper presents a combined solution to the Through-Silicon-Via (TSV) placement and mapping of cores to routers in a three-dimensional Network-on-Chip (NoC) design. It takes care of TSV geometries and communication requirements between cores. Comparison has been carried out with the recent 3D mapping results. Both static and dynamic performance have been considered. It shows that an intelligent placement of TSVs coupled with mapping can improve the performance significantly.

This paper presents a discrete particle swarm optimization (PSO)-based strategy to map applications on both 2-D and 3-D mesh-connected Networks-on-Chip. The basic PSO formulation has been augmented by: 1) running multiple PSOs and 2) deterministically generating a part of the initial population for PSO. The mapping results, in terms of the overall communication metric, have been compared with well-known techniques reported in the literature and also with exact methods built around integer linear programming (ILP). Our PSO-based results are superior to those from reported techniques. For smaller benchmarks, the results obtained are same as those corresponding to the ILP formulation, establishing the quality of the solution strategy.