This paper proposes a novel noise-shaping (NS) successive approximation register (SAR) based light-to-digital converter (LDC) for continuous multi-wavelength (MW) photoplethysmogram (PPG) monitoring. The proposed NS-SAR LDC employs a single-channel current-integration (CI) SAR quantizer with a three-channel passive NS loop filter performs time-multiplexed, low-power NS readout for MWPPG. The cascade integrator feedforward NS architecture features a passive nested feedback path, which contributes one additional NS order. The LDC enables a wide dynamic range (DR) through the high signal-to-noise-and-distortion ratio (SNDR), inherent AC gain control of the proposed CI NS-SAR, and a predictive threshold filter that compensates for large DC and drifting baseline currents induced by motion artifacts and interference light. Fabricated in a 180-nm standard CMOS process, the NS-SAR LDC consumes$26.5~\mu $W while achieving a SNDR of 95 dB and a total DR of 161.5 dB. The work is validated through finger MWPPG measurements using commercial PPG sensors.

This paper presents a low phase noise (PN) and low power voltage-controlled oscillator (VCO) for Sub-7 GHz applications. We introduce a novel Colpitts VCO with forward body bias technique designed to augment the negative transcon-ductance and to optimize PN. The integration of orthogonal-coupled VCO core is employed for a wide frequency tuning range (FTR) based on the previous frequency expansion developed by the dual-mode, with capacitor banks and varactors. Moreover, a switched varactor unit is employed to realize KVCO linearization and optimize the frequency regulation range. Designed in 65-nm CMOS, the measured results exhibit a low PN of -139.8 dBc/Hz at 10 MHz offset and a figure-of-merit (FOM) of 191.1 dBc/Hz from a 6.108 GHz carrier, while the FTR is 50.6% from 9.13 to 15.31 GHz. The proposed VCO consumes 2.78mW at 0.72-V supply voltage.

This paper presents a fast transient flipped-voltage-follower-based low-dropout regulator (FVF LDO) with improved gate buffer and level-triggered transient enhancement circuit (LTTEC) in a 22 nm process. The fast loop composed of an FVF and the improved gate buffer exhibits ultra-high bandwidth and high slew rate. The proposed LTTEC can supply additional sourcing or sinking current to reduce the undershoot or overshoot during load transitions. The introduced bulk driven technique can effectively improve the power supply rejection (PSR) performance. The proposed LDO achieves 0.25ns response time with simulated 40.0 mV undershoot voltage and 36.7 mV overshoot voltage for the load current transition between 100 µA and 20 mA within 0.1 ns.

This paper presents a first-order noise shaping (NS) successive approximation register (SAR) analog to digital converter (ADC) utilizing an innovative voltage controlled oscillator (VCO)-based charge-accumulation (CA) integrator. The proposed VCO-CA integrator is highly digital and dynamic, making it energy efficient and compatible with process scaling. Additionally, it can provide a highly linear gain thanks to the small amplitude of residual voltage and the proposed oscillation time control, avoiding the system nonlinearity problem in VCO-based integrators in conventional VCO-based$\mathrm {\Delta \Sigma }$ADCs. Combined with a pulse width (PW)-controlled tunable charge-accumulation circuit, it forms an active loop filter for the first-order NS-SAR ADC, resulting in an innovative fully dynamic VCO-based NS-SAR ADC that achieves a sharp noise transfer function (NTF) without any background gain calibration. The prototype ADC is implemented in a 65-nm GP CMOS process, achieving 77.7 dB SNDR and 79.9 dB DR over a bandwidth of 625 kHz. The total power consumption is$108.3~\mu $W, resulting in a Schreier figure of merit of 175.3 dB.

This paper introduces a highly efficient approach for the rapid design of high-performance pipelined-SAR ADCs. We leverage manual design expertise to extract and implement key block functionalities within a Python program, resulting in a substantial boost to the design and system iteration efficiency. Additionally, we employ advanced techniques, including neural networks, particle swarm optimization, and a fast DC-to-HDx prediction method, to further enhance the design process. To validate our approach, we applied it to the design of a 12-bit 1 GS/s 3-stage pipelined-SAR ADC in a CMOS 28 nm technology. The performance achieved by this design is comparable to the state-of-the-art ADCs in the field.

A noise-shaping successive approximation register analog-to-digital converters (NS-SAR ADCs) with sampling kT/C noise cancellation technique (SNC) in the cascaded integrator feedforward path (CIFF) is presented. A two-mode residual amplifier is used to achieve different gains in quantization noise shaping and sampling noise cancellation stages, effectively suppressing quantization noise and the kT/C noise. Compared to the SNC technique in the error feedback (EF) path, the proposed SNC-CIFF uses smaller SNC capacitor, reducing the time required for sampling noise extraction and improving the system’s tolerance to the two-mode residual amplifier gain fluctuations. Implemented in a 65 nm standard CMOS process, the proposed NS-SAR ADC achieves 10-bit quantization accuracy and 1-bit redundancy. Simulation results show that for a 0.8 pF input capacitance, it achieves a signal-to-noise-distortion ratio (SNDR) of 86.8 dB with sampling rate of 10 MS/s and power consumption of 107 uW, leading to 184.4-dB Schreier Figure of Merit (FOMs).

This brief presents an adaptive zero-current detector (ZCD) for the single-inductor multiple-output (SIMO) DC-DC converter with a full-wave current sensor. The innovative adaptive ZCD, which can be applied to the order power distribution control (OPDC) SIMO DC-DC converter, is designed, and it can accurately turn off the low-side power switch when the SIMO DC-DC converter operates in the discontinuous conduction mode. Besides, a new full-wave current sensor which contains only one sensing transistor is presented, and it can precisely sense the inductor current with a small delay. The SIMO DC-DC converter is designed and fabricated in a standard 65 nm CMOS process with output power ranges from 3.7 to 925 mW. The measured reverse current is reduced by up to 78.2%, and the measured light-load power efficiency is improved by up to 10%.

This paper presents a low-power high-accuracy key-word spotting (KWS) system based on analog passive switched-capacitor (SC) bandpass filters (BPF). The proposed system inno-vatively extracts the Mel-frequency cepstrum coefficient (MFCC) features with all-analog circuits, providing a better spotting performance than the present analog short-time amplitude or energy features under the same condition. At the circuit level, the analog-MFCC extraction includes the low-noise amplifier, BPF, squarer, integrator, and discrete cosine transformer. And thanks to the effective analog-MFCC features, the size of the fully-connected neural network (FCNN) classifier in our KWS system is enormously reduced. A high-order and fully-differential BPF is also proposed, achieving ultra-low power and high dynamic range by combining zero and pole generation stages rather than building stages separately in traditional ways. Fabricated in 0.18-$\mu \text{m}$CMOS, our filterbank of eight BPFs is measured with a power consumption of 83.2 nW, with a 69.7 dB dynamic range at 5% THD, having advantages over other SC BPFs with similar functions. The total power consumption of our feature extractor is 661.7 nW, achieving an accuracy of 96.6% in two-keyword spotting by an FPGA-based, 15k bit parameter FCNN with a 9.6$\mu \text{s}$latency.

Answering reachability queries is a fundamental graph operation. Considering that the size of the input graph has a great impact on query performance, there are studies focusing on reducing the graph size, such that queries can be answered over a smaller graph. Although the input graph can be compressed significantly by existing approaches, a good compression ratio does not always mean a positive effect on query performance. In this paper, we study graph reduction to accelerate reachability queries answering. We propose a novel graph reduction approach, namely RCN reduction, to compress the input graph into a smaller one. Let a be the compression ratio of the number of nodes in the reduced graph over that of the input graph, we show that based on our approach, the lower bound probability that a query q can be answered in constant time is 1-a^2. We show the difficulties of RCN reduction and propose efficient algorithms to improve the compression ratio. Based on the result of RCN reduction, we further propose a novel labeling scheme to accelerate queries answering. We confirm the efficiency of our approach by extensive experimental results for graph reduction and reachability queries processing using 20 real datasets.

We study graph reduction to accelerate reachability queries answering. We propose a novel graph reduction approach, namely RCN reduction, to reduce the input graph$G$of$\vert V\vert$nodes into a smaller one with$\vert V^{r}\vert$nodes. Assume that the probability of a node of$G$to be a query node is$1/\vert V\vert$, we show that based on our approach, the lower bound probability that a query$q$can be answered in constant time is$1-(\frac{\vert V^{r}\vert}{\vert V\vert})^{2}$, denoting that the smaller the reduced graph, the larger the probability that$q$can be answered in constant time. We show the difficulties of RCN reduction and propose efficient algorithms to improve the reduction ratio. We confirm the benefits of our approach by rich experimental results using real datasets.

A Wireless Power Transfer (WPT) system with a simplified Receiver (RX) is proposed for Implantable Medical Devices (IMDs) in this paper. This system utilizes LCC-S compensation of the coupling coils for rough voltage regulation and global control for fine voltage regulation and high efficiency. To further reduce the cost, data transmission is realized based on the coupling coils. This method minimizes the components in the receiver, reducing the receiver volume and making it very suitable to wirelessly power the IMDs. A prototype is built up and the board-level experimental results validate the effectiveness of the proposed method. With the modulation signal based on Load Shift Keying (LSK), data communication through the energy link and adjustment of transmitting power in primary side, the system can adjust output voltage automatically. From the measurement results, the system power efficiency can achieve 49% at 5.1 V output voltage.

This manuscript presents an ultra-low power acoustic feature extractor for always-on voice activity detection (VAD). It extracts voice features by a 10-band passive switched-capacitor (SC) bandpass filter (BPF) bank and digitizes the features using a passive SC envelope-to-digital converter at the low feature rate. The SC feature extractor minimizes the impact of process-voltage-temperature (PVT) variation at the circuit level, and is thereby free from costly chip-wise training or calibration while at the same time being capable of achieving a classification accuracy matching the state of the arts. Experimental results from a VAD feature extractor prototype fabricated in a 0.18-μm CMOS validate the effectiveness of the proposed techniques. It achieves an averaged 90%/86% speech/non-speech hit rates at 10 dB signal-to-noise ratio for all tested chips based on a universal classifier trained with data from one chip. The feature extractor is mostly passive and thus a low power consumption of 270 nW is achieved. In addition, the proposed feature extractor is frequency-scalable, which allows power-efficient multi-purpose acoustic system implementation.

This paper presents a high-frequency pulse stimulation (HFPS) output stage of neuro-stimulator with extended average output current range and high power efficiency. The output stage features two parallel buck-boost converters without any filter capacitor at the output node. Compared with HFPS output stage with only one converter, the proposed circuit doubles the maximum average current by staggering the output of two converters. Compared with traditional voltage mode stimulation (VMS), HFPS improves the power efficiency by discharging the inductor current through the tissue load directly, rather than through a filter capacitor with constant voltage. Besides, the control circuit for the proposed HFPS is much simpler than that of traditional VMS converter, which reduces the current consumption significantly and thus improves the efficiency. Test results confirm that with staggered output of two parallel converters, the maximum average current is doubled. The maximum energy efficiency of the proposed HFPS is 76.4%.

Top-K subgraph matching is one of the hot research issues in graph data management, which is to find, from the data graph, K subgraphs isomorphic to the query graph with the largest sum of weights. The existing methods of Top-K subgraph matching on large graphs usually use the filter-and-verify strategy. However, they all suffer from inefficiency in both stages. In the filtering stage, there exists repeated enumeration of vertices and the excessive memory cost of the filtering. In the verification stage, there exists redundant verification. Regarding to the above problems, we propose to use the preprocessing of the graph compression based on equivalent vertices to reduce the enumeration. In the filtering stage, we propose to reduce the memory cost by only considering the direct neighbors. In the verification stage, we take the vertex with the minimum number of candidate vertices in the query graph as the start vertex of the matching order, and use the idea of Ranking While Matching (RWM) to terminate the execution of the algorithm as early as possible by estimating the upper bound of the weights, so as to reduce redundant verification and improve the overall performance. Finally, the experimental results show that our method is much more efficient than existing methods in compression and the processing time.

In this paper, a low power three-stage CMOS amplifiers with 375x capacitive load (Ci) drivability will be presented. By employing the cascode Miller compensation, the non-dominant complex pole frequency is extended effectively and the physical size of the compensation capacitors is reduced. A local Q-factor control (LQC) loop is introduced to optimize the Q-factor when loading capacitance Cl changes dramatically, which is essential to improve settling performance. Also, a left-half-plane (LHP) zero is created to increase the phase margin and a feed-forward transconductance stage is paralleled to improve the slew rate (SR). Implemented in standard 0.13-μm CMOS technology, the amplifier can handle 4 pF to 1.5 nF capacitive load with at least 0.88-MHz unity-gain frequency (UGF) while consuming as low as 24.0 μW of quiescent power at 1.0-V supply voltage.

An improved Nauta transconductor, with output resistance for differential-mode output signals insensitive to process and tuning voltage variations, is presented in this paper. Comparing with the classical Nauta transconductor, the proposed transconductor introduces 4 auxiliary inverters only. It can increase the differential-mode output resistance, and keep the common-mode output resistance nearly no changed at the same time. The proposed transconductor has been implemented in a 7th-order transconductance-C (gm-C) band-pass filter (BPF) in a standard 0.18-μm CMOS technology. The proposed filter has achieved a bandwidth of 20 MHz under a 15-MHz center frequency. Monte Carlo simulation results show that with the same tuning voltage range, the gain deviation of the filter with proposed transconductors is reduced 4.4 dB comparing with the counterpart based on classical Nauta transconductors, and the sensitivity of the quality (Q) factor of filter poles to tuning voltage is also significantly reduced. Measurement results show that the pass-band ripple of the proposed filter is reduced 1 dB, and the stop-band attenuation is reduced 8 dB at 30 MHz.

Answering reachability queries is one of the fundamental graph operations. The existing approaches build indexes and answer reachability queries on a directed acyclic graph (DAG) G, which is constructed by coalescing each strongly connected component of the given directed graph G into a node of G. Considering that G can still be large to be processed efficiently, there are studies to further reduce G to a smaller graph. However, these approaches suffer from either inefficiency in answering reachability queries, or cannot scale to large graphs.

This paper presents a successive-approximation-register (SAR) analogue-to-digital converter (ADC) using a tri-level switching scheme named as reverse VCM-based scheme which maintains good linearity without any driving and accuracy requirements on VCM. A 10-bit SAR ADC is designed in a 0.18 CMOS technology. With a unit capacitor size of 17.2 fF, the ADC consumes 41.9 μW from a 1.8 V voltage supply. The measured signal-to-noise-plus-distortion ratio (SNDR) is 59.6 dB at 2 MS/s. The figure-of-merit (FOM) is 26.9 fJ/conv.-step.

Intrabody communication has been of great research interest in recent years. This paper proposes a novel, compact but accurate body transmission channel model based on RC distribution networks and transmission line theory. The comparison between simulation and measurement results indicates that the proposed approach accurately models the body channel characteristics. In addition, the impedance-matching networks at the transmitter output and the receiver input further maximize the power transferred to the receiver, relax the receiver complexity, and increase the transmission performance. Based on the simulation results, the power gain can be increased by up to 16 dB after matching. A binary phase-shift keying modulation scheme is also used to evaluate the bit-error-rate improvement.

Efficiently answering XML keyword queries has attracted much research effort in the last decade. The key factors resulting in the inefficiency of existing methods are thecommon-ancestor-repetition(CAR) andvisiting-useless-nodes(VUN) problems. To address the CAR problem, we propose agenerictop-downprocessing strategy to answer a given keyword query w.r.t. LCA/SLCA/ELCA semantics. By “top-down”, we mean that we visit allcommon ancestor(CA) nodes in a depth-first, left-to-right order; by “generic”, we mean that our method is independent of the query semantics. To address the VUN problem, we propose to use child nodes, rather than descendant nodes to test the satisfiability of a node$v$w.r.t. the given semantics. We propose two algorithms that are based on either traditional inverted lists or our newly proposed LLists to improve the overall performance. We further propose several algorithms that are based on hash search to simplify the operation of finding CA nodes from all involved LLists. The experimental results verify the benefits of our methods according to various evaluation metrics.

This paper presents a novel low-voltage CMOS smart temperature sensor targeted for VLSI thermal management. A polyresistor is used as the sensing element and digitization is performed in the time domain. The proposed temperature-sensing concept can be realized with simple circuits that operate at low supply voltages, which are compatible with the digital circuits in VLSI systems. Fabricated in 90-nm CMOS, the sensor can operate with a supply voltage as low as 0.8 V and features a supply sensitivity of 4°C/V. After 50-sample moving-average and a two-point calibration at 25°C and 45°C, the design achieves an inaccuracy of -0.6°C/0.8°C over -40°C-125°C. It dissipates only 11.8 uW at a sampling rate of 5 kS/s from a 0.9-V nominal supply.

This paper presents a low power, long-transmission distance, high data rate intrabody communication (IBC) analog receiver front end (RFE). First, to optimize the transmission performance, conventional transmission line analysis scheme is creatively adopted to the IBC design to characterize the body channel. Second, switched-capacitor filters based on sampling rate boosting technique are adopted for higher accuracy and lower power consumption. Third, a novel RFE topology is proposed to further enhance the IBC performance. The new RFE is designed and fabricated in a standard 180-nm CMOS process. Measurement results show that the RFE can successfully transmit data spanning the whole human body, around 180 cm, which is one of the longest transmission distances reported in related literatures. Furthermore, it reaches a maximum data rate of 2.5 Mb/s with a bit error rate less than 1e-7 and consumes 5.4 mW from a 1.8 V supply. The proposed RFE compares favorably to similar reported works.

In this paper, a new overshoot cancellation method is presented for comparator-based pipelined ADCs. By introducing charging and discharging operations in two adjacent stages, the large overshoot in each stage can be either tolerated as sub-ADC error or cancelled out with each other. Applying this concept, a 10-bit pipelined ADC has been designed and simulated in a 0.18-μm CMOS process. It achieves 57.2dB SNDR at 20MS/s and consumes 2.6mW under 1.8 V supply, resulting in an ENOB of 9.2-bit and an FOM of 0.221 pJ/Conv.-step.

Flash disks are being widely used as an important alternative to conventional magnetic disks, although accessed through the same interface by applications, their distinguished feature, i.e., different read and write cost in the aspects of time, makes it necessary to reconsider the design of existing replacement algorithms to leverage their performance potential. Different from existing flash-aware buffer replacement policies that focus on the asymmetry of read and write operations, we address the “discrepancy” of the asymmetry for different flash disks, which is the fact that exists for a long time, while has drawn little attention by researchers since most existing flash-aware buffer replacement polices are somewhat based on the assumption that the cost of read operation is neglectable compared with that of write operation. In fact, this is not true for current flash disks on the market. We propose an adaptive cost-aware replacement policy (ACR) that uses three cost-based heuristics to select the victim page, thus can fairly make trade off between clean pages (their content remain unchanged) and dirty pages (their content is modified), and hence, can work well for different type of flash disks of large discrepancy. Further, in ACR, buffer pages are divided into clean list and dirty list, the newly entered pages will not be inserted at the MRU position of either list, but at some position in the middle, thus the once-requested pages can be flushed out from the buffer quickly and the frequently-requested pages can stay in buffer for a longer time. Such mechanism makes ACR adaptive to workloads of different access patterns. The experimental results on different traces and flash disks show that ACR not only adaptively tunes itself to workloads of different access patterns, but also works well for different kind of flash disks compared with existing methods.