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Junchao Yan

dblp:26/8118 · DBLP profile ↗
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4ranked-venue papers
0as first author
0since 2021 · last 2020
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3Human-computer interaction and ubiquitous computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 67% Electronic design automation · 33%
Artificial intelligence
1 paper
Deep learning architectures and training · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › machine learning accelerator
CNN accelerator
0.412019
SqueezeFlow: A Sparse CNN Accelerator Exploiting Concise Convolution Rules · IEEE Trans. Computers 2019
Electronic design automation › system-level design
dataflow design
0.412019
SqueezeFlow: A Sparse CNN Accelerator Exploiting Concise Convolution Rules · IEEE Trans. Computers 2019
Hardware accelerators and domain-specific architectures › machine learning accelerator › CNN accelerator
sparse CNN accelerator
0.412019
SqueezeFlow: A Sparse CNN Accelerator Exploiting Concise Convolution Rules · IEEE Trans. Computers 2019
Machine learning › Deep learning architectures and training
convolutional neural network
0.112019
SqueezeFlow: A Sparse CNN Accelerator Exploiting Concise Convolution Rules · IEEE Trans. Computers 2019

Methods — techniques the papers use, named apart from their topics

concise convolution rules · 0.8PT-OS-sparse dataflow · 0.8
YearPublicationVenuePosition
2020 BZIP: A compact data memory system for UTXO-based blockchains
Shuhao Jiang, Shijun Gong, Junchao Yan, Guihai Yan, Yi Sun 0004, Xiaowei Li 0001
J. Syst. Archit.4
2019 TNPU: an efficient accelerator architecture for training convolutional neural networks
abstract
Training large scale convolutional neural networks (CNNs) is an extremely computation and memory intensive task that requires massive computational resources and training time. Recently, many accelerator solutions have been proposed to improve the performance and efficiency of CNNs. Existing approaches mainly focus on the inference phase of CNN, and can hardly address the new challenges posed in CNN training: the resource requirement diversity and bidirectional data dependency between convolutional layers (CVLs) and fully-connected layers (FCLs). To overcome this problem, this paper presents a new accelerator architecture for CNN training, called TNPU, which leverages the complementary effect of the resource requirements between CVLs and FCLs. Unlike prior approaches optimizing CVLs and FCLs in separate way, we take an alternative by smartly orchestrating the computation of CVLs and FCLs in single computing unit to work concurrently so that both computing and memory resources will maintain high utilization, thereby boosting the performance. We also proposed a simplified out-of-order scheduling mechanism to address the bidirectional data dependency issues in CNN training. The experiments show that TNPU achieves a speedup of 1.5x and 1.3x, with an average energy reduction of 35.7% and 24.1% over comparably provisioned state-of-the-art accelerators (DNPU and DaDianNao), respectively.
Guihai Yan, Wenyan Lu, Shuhao Jiang, Shijun Gong, Jingya Wu, Junchao Yan, Xiaowei Li 0001
ASP-DAC7
2019 SqueezeFlow: A Sparse CNN Accelerator Exploiting Concise Convolution Rules
abstract
Convolutional Neural Networks (CNNs) have been widely used in machine learning tasks. While delivering state-of-the-art accuracy, CNNs are known as both compute- and memory-intensive. This paper presents the SqueezeFlow accelerator architecture that exploits sparsity of CNN models for increased efficiency. Unlike prior accelerators that trade complexity for flexibility, SqueezeFlow exploits concise convolution rules to benefit from the reduction of computation and memory accesses as well as the acceleration of existing dense architectures without intrusive PE modifications. Specifically, SqueezeFlow employs a PT-OS-sparse dataflow that removes the ineffective computations while maintaining the regularity of CNN computations. We present a full design down to the layout at 65 nm, with an area of 4.80 mm2and power of 536.09 mW. The experiments show that SqueezeFlow achieves a speedup of 2:9× on VGG16 compared to the dense architectures, with an area and power overhead of only 8.8 and 15.3 percent, respectively. On three representative sparse CNNs, SqueezeFlow improves the performance and energy efficiency by 1:8× and 1:5× over the state-of-the-art sparse accelerators.
Shuhao Jiang, Shijun Gong, Jingya Wu, Junchao Yan, Guihai Yan, Xiaowei Li 0001
IEEE Trans. Computers5
2013 An exploratory survey on the use of computation in undergraduate engineering education
abstract
Advances in computing contribute to science and engineering discovery, innovation, and education by facilitating representations, processing, storage, analysis, simulation, and visualization of unprecedented amounts of experimental and observational data to address problems that affect health, energy, environment, security, and quality of life. In spite of the emerging importance of the role of computing in engineering, a well-recognized shortage of scientists and engineers who are adequately prepared to take advantage of, or contribute to, such highly interdisciplinary, highly computational scientific challenges is evident. This exploratory study identifies how computation is integrated in the engineering disciplines at the undergraduate level. The research question is: How engineering professors integrate computation as part of their disciplinary undergraduate courses? This study reports anonymous survey responses of thirty-nine engineering and engineering technology faculty members who identified themselves as integrating computation as part of their undergraduate courses. Results indicate that most of the faculty members used computation for the solution of complex calculations, for conducting simulations, and for design purposes. Further research is required in order to identify and validate appropriated pedagogical practices to integrate computation as part of disciplinary courses.
Alejandra J. Magana, Camilo Vieira 0001, Francesca G. Polo, Junchao Yan
FIE4