Physically Unclonable Functions (PUFs) need error correction whilst regenerating Secret Keys in cryptography. The proposed 8-Transistor (8T) PUF, which coordinates with the power gating technique, can significantly accelerate a single evaluation cycle 1000 times faster than$\mathbf{6}\mathbf{T}$-SRAM PUF does with a 12.8% area increase. This design enables multiple evaluations even in the key regeneration phase in field, hence greatly reducing the number of errors and the hardware penalty for error correction. The$\mathbf{8T}$PUF derives from the$\mathbf{6}\mathbf{T}$SRAM. It is built to eliminate data retention swiftly and maximise physical mismatches. And a two-phase power gating module is designed to provide controllable power-on/off cycles rapidly for the chosen PUF clusters in order to facilitate statistical measurements and curb the in-rush current, thereby enhancing PUF entropy and security. An architecture of the power-gated PUF is developed to accommodate fast multiple evaluations. Post-layout Monte Carlo simulations were performed with Cadence, and the extracted PUF Responses were processed with Matlab to evaluate the 8T PUF performance and statistical metrics for subsequent inclusion into PUF Responses.

With technology scaling, the vulnerability of combinational circuits is increased, so evaluating their reliability becomes an essential demand. In this paper a simple yet effective method is proposed to derive the reliability of a combinational circuit. The idea of this method is to prevent the complexity of the traditional methods that use multi-iteration statistical procedures. This goal is achieved by dividing the problem into two parts, one describing the cause of the error, and the other part is involved on the circuit under test. The cause of the error is represented as a stochastic model of the interference, which can be considered as a fixed model for a specific design. The other part is derived by applying the stochastic fault model on the circuit under test using a simulation tool. A critical values are obtained by the second part, these values are the boundaries between two regions; error region and error-free region. The next step is to find the probability of error-free region by using some mathematical procedures. The probability of the error-free region can be interpreted as a reliable operating mode of that circuit. For the sake of simplicity, the proposed method is applied to a chain of inverters. A trade-off relation between energy, performance and reliability is obtained. A slow stage is added to the circuit under test to see its effect on the reliability of the circuit.

A new method of evaluating the reliability of combinational circuits is proposed, this method uses two levels of characterisation: a Stochastic Fault Model (SFM) of the component library and a design-specific Critical Vector Model (CVM). The idea is to move the high-complexity problem of stochastic characterisation of parameters into the generic part of the design process, and do it just once for a great number of the specific designs. The SFM captures variations of the vector of parameters of a library component fault model, those causing a transient fault at the component output; it is meant to be supplied by the foundry, similar to timing library files. The CVM is derived by a limited number of simulation runs on the specific design, and represents the boundary between the erroneous and error-free operation, w.r.t. the vector of parameters of each component. The probability of error-free operation is subsequently calculated by jointly using SFM and CVM. The method is demonstrated on a chain of inverters for simplicity, and subsequently applied to a 3-bit full adder. A complex three-way trade-off between energy, performance and reliability is explored. The method is meant to serve as a basis for design-time reliability evaluation and runtime power-reliability management. A slow stage is added to the circuit under test to improve its reliability.

A wireless sensor network (WSN) employed to serve smart city applications is usually located in a vast and vulnerable territory. In order to secure vital and critical information, the security requirements of data confidentiality, authenticity and availability should be guaranteed. One of the leading key management schemes is based on using location information to generate security credentials. However, existing location-dependent schemes have disadvantages related to cell capture caused by a threshold number of nodes (e) being compromised. This paper presents a location-dependent key management protocol with a random selected cell reporter, LKMP-RSCR, where a set of cell reporters are selected randomly by the base station (BS) to provide a third level of report endorsement. In the LKMP-RSCR, an adversary would need to compromise all cell reporters in addition to endorsement (e) nodes to capture a particular cell. The LKMP-RSCR is presented and evaluated using an extensive analysis that shows a significant enhancement achieved in comparison with LEDS and MKMP schemes in terms of data confidentiality (85%), authenticity (35%) and availability (85%).

With increased reliance on encryption for e-commerce, communications and data storage, new techniques are constantly being developed to meet the demand for secure encryption systems requiring higher levels of security and integrity. A significant aspect of integrity is the diffusion and avalanche effect, which is measured by its sensitivity to a single bit change between the cipher text and the plaintext. This effect should yield a catastrophic result which is measurable and can therefore be readily assessed for its suitability as part of a security system. This paper measures the standard one-dimensional implementations of the generalized new Mersenne number transform suite for its suitability in security applications. The generalized suite is expanded from the existing new Mersenne number transform, by the addition of two new transforms, which have yet to be fully assessed in this aspect. The two new transforms offer the same long power-of-two run lengths and efficient calculations over a field of integers modulo a Mersenne prime. Sharing similar characteristics with the original transform, they also have the cyclic-convolution property, suggesting that they too can wield significant impact in the fields of image-, signal-processing as well as cryptography.

Soft errors are a serious concern in state holder circuits at they can cause temporarily malfunctions. C-elements are one of the state holders that are widely used in asynchronous circuits. In this paper, our investigations focus on the vulnerability of different latch types based on C-elements with respect to soft errors. Our aim is to design single event upset (SEU) tolerant latch that has the capability of both detecting and correcting soft errors based on converting single rail to dual-rail configuration and Razor flip flop implementation. In the event of an SEU hitting sensitive nodes and causing the state to temporarily change, an error is generated and a shadow latch restores the correct data. We have demonstrated the functionality of our proposed latch by simulating the design using UMC90nm technology. We also measured error rate of our proposed latch by using an Altera Cyclone II FPGA board. We have obtained the voltage dependence of the error rates. The results show that our proposed latch has less than 1.5% faults propagated at the output.

A new balanced library is presented which consists of novel mixed 1-of-2 and 1-of-4 components based on N-nary logic. Cryptographic circuit specifications are refined and passed to optimization and mapping tools for mapping to a library of power-balanced components. Logic optimization tools are then applied to generate secure synchronous circuits for layout generation. This paper presents a new technique for evaluating the security of such circuits in particular those which offer a higher level of protection. A security metric is introduced which is based on the common selection function that is widely used in differential power analysis attacks and a correlation measure similar to the one used in correlation power analysis attacks. This is used to compare the security level for these kinds of balanced circuits that are more difficult to attack. This paper shows that the circuits generated are more efficient and can offer more security than alternative solutions.

Asynchronous interfaces, being a popular way of dealing with timing closure problems in deep submicron SoCs, pose a serious problem for on-line testing. Their behavior is specified not as a traditional clocked automaton, but as an asynchronous protocol with timing which depends on the clocks of the communicating blocks, wire and gate delays. The problem is exacerbated by the use of non-encoded bundled data buses, whose transitions cannot be reliably detected, as opposed to very expensive self-timed data encodings. This paper presents a further development of our low-cost checkers for asynchronous handshake protocol, which now support bundled data and are interfaced to the scan chains to assist diagnosis and debugging. Further reduction of area requirements for the delay elements, possibilities to define separate delays for each protocol phase, test results collection and checking the timing relationships between the handshake and the data signals are discussed. An application of the data transition detectors to checking of synchronous SDR/DDR protocols is shown.

A technique of constructing dual-rail muller pipelines tolerant to transient faults is proposed. The pipeline datapath is either an NCL-D or NCL-X circuit. A dedicated controller implements the error recovery protocol, which significantly improves fault tolerance with respect to the earlier rail synchronization method. A case study featuring transient fault simulation is presented.

A method for an automated synthesis of low-latency asynchronous controllers is presented. It is based on a direct mapping approach and starts from an initial specification in the form of a signal transition graph (STG). This STG is split into a device and an environment, which synchronize via a communication net that models wires. The device is represented as a tracker and a bouncer. The tracker follows the state of the environment and provides reference points to the device outputs. The bouncer communicates with the environment and generates output events in response to the input events according to the state of the tracker. This two-level architecture provides an efficient interface to the environment and is convenient for subsequent mapping into a circuit netlist. A set of optimization heuristics is developed to reduce the latency and size of the circuit. As a result of this paper, a software tool called OptiMist has been developed. Its low algorithmic complexity allows large specifications to be synthesized, which is not possible for the tools based on state-space exploration. OptiMist successfully interfaces conventional EDA design flow for simulation, timing analysis, and place-and-route

A logic design style known as phase difference-based logic (PDBL) has several benefits with respect to security and testing. An existing design method for PDBL circuits has so far been lacking an important component, a register. In this paper, we present the design of a speed independent PDBL register and a timed PDBL register, which can be used in asynchronous or synchronous circuits. Comparisons are presented in terms of speed, size, and power consumption.

A new low-cost low-complexity checker for online testing of asynchronous interfaces in globally-asynchronous locally-synchronous circuits is proposed. The solution is fully based upon the standard gate libraries. The checker itself is fully offline testable. It also provides a fault-locating functionality, which is achieved by combining the online mode with scan techniques

Comparison between synchronous and asynchronous models leads to a protocol-based fault model for asynchronous circuits. Protocol monitoring of the control path is separated from data comparison in the data path. A novel protocol decomposition technique is used to extract simple protocols from behaviour of a complex circuit. This technique is implemented as a software tool. An asynchronous checker model, implementation and simulation results are presented. Coverage of internal faults of the checker is calculated

Cryptographic chips are highly susceptible to fault injection and power analysis attacks, which easily lets an attacker gain secret keys intended to be secure. In addition to these issues, testability circuitry is frequently manipulated to induce faults and undesired behavior. When power-balanced dual-rail (1-of-2) logic, a return-to-spacer protocol and power-balanced totally self checking checkers with redundant transistors are used together, they significantly improve and enforce security; simultaneously facilitating secure on-line testability. In this paper, we propose and show how to implement such circuits in cryptographic chips, the fruits of which are high reliability, testability and security.

The problem of on-line testing of asynchronous circuits is analyzed, several infrastructures are proposed and a self-checking tree checker is designed. The checker uses on-demand self-test, which reduces power consumption and guarantees bounded self-test period. Objects under test are tested by observing protocols at their primary inputs and outputs. The checker does not slow down the functional system, as it only samples the signals. The protocols are checked by identifying enabled and refused signal transitions in each state of the system. The fault coverage of internal faults of the checker is calculated. Simulation results are included.

Dual-rail encoding, return-to-spacer protocol, and hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g., all-zeros, which gives rise to energy balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in every clock cycle regardless of the transmitted data values. To generate these dual-rail circuits, an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the advanced encryption standard (AES) have been simulated and compared in order to evaluate the method and the tool.

Communication-centric design is a key paradigm for systems-on-chips (SoCs), where most computing blocks are predesigned IP cores. Due to the problems with distributing a clock across a large die, future system designs are more asynchronous or self-timed. For portable, battery-run applications, power and pin efficiency is an important property of a communication system where the cost of a signal transition on a global interconnect is much greater than for internal wires in logic blocks. We address this issue by designing an asynchronous communication system aimed at power and pin efficiency. Another important issue of SoC design is design productivity. It demands new methods and tools, particularly for designing communication protocols and interconnects. The design of a self-timed communication system is approached employing formal techniques supported by verification and synthesis tools. The protocol is formally specified and verified with respect to deadlock-freedom and delay-insensitivity using a Petri-net-based model-checking tool. A protocol controller has been synthesized by a direct mapping of the Petri net model derived from the protocol specification. The logic implementation was analyzed using the Cadence toolkit. The results of SPICE simulation show the advantages of the direct mapping method compared to logic synthesis.

Summary form only given. A new method, algorithms and tool for the visualisation of a finite complete prefix (FCP) of a Petri net (PN) or a signal transition graph are presented. A transformation is defined that converts such a prefix into a two-level model. At the top level, it has a finite state machine (FSM), describing modes of operation and transitions between them. At the low level, there are marked graphs, which can be drawn as waveforms, embedded into the top level nodes. The models of both levels are abstractions traditionally used by electronics engineers. The resultant model is completed trace equivalent to the original prefix. Moreover, the branching structure of the latter is preserved as much as possible.