Qinsong Qian

dblp:26/8519 · DBLP profile ↗
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4ranked-venue papers
0as first author
4since 2021 · last 2026
0000-0002-1573-7342ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 4 since 2021
YearPublicationVenuePosition
2026 A Reinforcement Learning Co-Simulation Platform for Event-Triggered and Variable-Frequency Power Converter Control
Minggang Chen, Qinsong Qian, Weifeng Sun 0001
ISCAS3
2024 A High-Switching-Frequency Multi-Mode Four-Switch Buck-Boost Converter Empowered by a 400-MHz Bandwidth Two-Stage Operational Amplifier
abstract
This paper introduces the utilization of a high-bandwidth rail-to-rail operational amplifier in switching converters, which opens the door to advancing switching converters towards higher switching frequencies. As the switching frequency increases, the signal within switching converters also rises, frequently surpassing the switching frequency itself. Consequently, a high-bandwidth amplifier becomes imperative. The proposed operational amplifier is fabricated using the 0.18-μm BCD process and integrated into the voltage-seconds balance circuit of a multi-mode four-switch buck-boost (FSBB) converter for validation purposes. Post-layout simulation results demonstrate that the amplifier achieves a bandwidth of 400 MHz with a quiescent current of 140 μA. Furthermore, the amplifier is applied in a high-frequency four-switch buck-boost converter to meet the demands of high switching frequencies. The input voltage for the four-switch buck-boost ranges from 150 V to 420 V, while the output voltage is maintained at 28 V. The excitation inductance value is only 5 μH. Simulation results demonstrate that the switching frequency can be enhanced to 2 MHz with the use of the high-bandwidth operational amplifier.
Wangchen Fan, Qinsong Qian, Weifeng Sun 0001, Zhongyuan Fang
ISCAS2
2024 Novel Sensorless Current Multimode Control for PSR Double-Clamp ZVS (DCZVS) Flyback Converter in DCM and CrCM
abstract
There are two drawbacks in the previous tri-mode variable-frequency peak current mode (VFPCM) control for primary side regulation (PSR) double-clamp zero voltage switching (DCZVS) flyback converter: firstly, the current-sense resistor leads to non-negligible loss at high power and instability at high frequency; secondly, the previous tri-mode control suffers from poor dynamic performance and lacks accurate small-signal model in various control modes. In this paper, a novel sensorless current quad-mode control is proposed, which eliminates the current-sense resistor by input voltage feed-forward and improve the dynamic performance by introducing hybrid mode (HYM) and seamless mode-switch. In addition, a unified small-signal model of the four control modes is derived in the paper, which explains the high dynamic performance of the introduced HYM. The proposed sensorless current quad-mode control and the unified small-signal model are validated on a 16-50V input and 28V/320W output experimental prototype. Compared with the traditional tri-mode peak current mode control, the undershoot recovery time and overshoot recovery time of the proposed control scheme are reduced from 12ms to 2.0ms and 12ms to 1.6ms, respectively.
Qinsong Qian, Weifeng Sun 0001
IEEE Trans. Circuits Syst. I Regul. Pap.4
2024 A 200-V Half-Bridge Monolithic GaN Power IC With High-Speed Level Shifter and dVS/dt Noise Immunity Enhancement Structure
abstract
Benefiting from the gallium nitride (GaN) monolithic process, a half-bridge power IC can fully unlock the high-speed capabilities of GaN devices by integrating drive circuits and power switches on the same die. However, the high operating frequency of the GaN system puts forward higher requirements on the delay and reliability of the level shifter, which serves as the key component for the half-bridge power IC. This work develops a 200-V half-bridge monolithic GaN power IC, adopting an efficient and concise level-shifting solution to mitigate the adversely affecting on speed caused by the absence of p-type devices in GaN processes. In addition, this design includes a noise immunity enhancement structure, which eliminates$\text {d}V_{S}/\text {d}t$noise without compromising response time. The proposed GaN power IC has been implemented on a 1-$\mu \text{m}$GaN-on-silicon process, and experimental results have already been performed to verify its outstanding characteristics.
Qianheng Dong, Yutao Ying, Deyuan Song, Jing Zhu 0006, Weifeng Sun 0001, Qinsong Qian, Denggui Wang
IEEE Trans. Very Large Scale Integr. Syst.8