While it is easy to automate coverage data collection, it is a time consuming/difficult/expensive manual process to analyze the data so that it can be acted upon. The goal of the approaches discussed in here is to reduce the cost and barrier to entry of using coverage data analysis in large-scale projects by categorizing and prioritizing coverage changes to avoid the need for manual review at every release or on every build.Differential coverage and date binning are methods of combining coverage data and project/file history to determine if goals have been met and to identify areas of unexercised code which should be reviewed. These methods can be applied to any coverage metric which can be associated with a location - statement, function, expression, toggle, etc. - and to any language, including both software (C++, Python, etc.) and hardware description languages (SystemVerilog, VHDL).The approach is realized in diffcov1, a recently released open-source tool.

System-level verification of a modem product involves ensuring both the hardware and firmware work correctly and that the product meets signal performance requirements at low cost. In many ways, the firmware problem is harder - or at least more open-ended. We discuss a development methodology based on automatic generation and reusable components that has been used to implement several generations of software-defined radio (SDR) modem SOCs. Automation both ensures consistency between models and tools and enables fast turnaround when something changes.

The goal of test synthesis is to create a circuit which is completely testable under a design-for-test (DFT) methodology while meeting performance and area requirements. It includes such steps as testability design rule checking and automated repair of identified violations. Potential violations include clock and asynchronous circuitry which do not operate in a manner consistent with the chosen methodology and tools. Repair is performed by transforming the network through the insertion of additional logic to perform test functions (a scan chain, for example) and mapping this logic into the implementation technology, without affecting the original, system mode operation of the network. This paper discusses the concept of test synthesis constraints which embody the conditions under which the circuit must operate in order to be fully testable. Based on the constraints, the circuit is transformed using algorithms similar to those of automatic test pattern generation. Rather than adding entirely new hardware, existing system logic and connectivity is used to implement test functions wherever possible. Results produced by a prototype implementation indicate that test logic can be inserted into a network with very little performance or area overhead.

Necessary, nonconflicting, and arbitrary assignments can be distinguished during algorithmic test pattern generation. The identification of necessary and nonconflicting assignments is algorithmic in the sense that there is no element of choice or luck in the computation, no reliance on heuristics, and no possibility of these assignments causing a backtrack if the fault is testable. This paper presents algorithms based on the mathematical properties of images and inverse images of set functions to define reduction and tendency lists in combinational logic circuits, used to identify necessary and nonconflicting assignments, respectively. Issues relating to the efficient implementation of these algorithms are addressed from both a theoretical and practical perspective. Experimental results obtained on a variety of benchmark circuits show that algorithmic assignment identification can be used to reduce or eliminate backtracking in automatic test pattern generation.>

The authors present a novel test pattern generation algorithm which uses the concept of necessary assignments to reduce or eliminate backtracking in automatic test pattern generation. Necessary assignments are those which must be made in order to find a test pattern; without them the search is guaranteed to fail. The algorithm is based on the mathematical concept of images and inverse images of set functions. In order to take advantage of formal concepts developed for Boolean algebras, the algorithm uses a 16-valued algebra. It has been used to generate test patterns for all faults in a variety of benchmark circuits. Experimental results indicate that the algorithm is particularly efficient at redundancy identification, which is often a problem for conventional test pattern generation algorithms. The benefits of a 16-valued system are illustrated through examples of faults which are not properly handled by conventional 5- or 9-valued systems.>

A novel approach to matched field processing of very large array is developed and illustrated by example. The full array is divided into subarrays, and plane-wave beamforming is performed on the subarrays. A technique is presented for dividing the array into subarrays based on the sound speed profile so that plane-wave beamforming is appropriate on the subarrays. The procedure leads to significant simplification, since almost all of the performance can be achieved by optimum combinations of a very small number of beams.>

A comparative study is presented of different methods of calculating multiple fault coverage and aliasing probability measures. The objectives are to describe the ways that these ratios are defined to give them a physical interpretation, and to separate the discussion of how to define the measure from how the measure might be actually obtained or calculated. The interpretation, accuracy, and applicability of the measures are discussed.>

A general technique is described to represent stuck-open faults in CMOS networks by transition (slow-to-rise and slow-to-fall) faults in equivalent gate-level circuits. Generally, CMOS complex gate require two gate-level representations: one for the n- part and another for the p-. The two representations may not be dual. After transformation, an algorithm based on the GEMINI logic system is used to determine the stuck-open fault coverage of a given test set. Multiple stuck-open faults are handled implicitly. Thus, results are not invalidated in the presence of untested or untestable faults. Robust test sets can be generated easily. The method can be used both for test generation and for fault diagnosis. Experimental results for multiple stuck-open fault coverage for ten benchmarking circuits are presented and compared. In particular, coverage figures for both robust and nonrobust test sets are presented.>

The authors present a fault coverage analysis method for test generation and fault diagnosis of large combinational circuits. Input vectors are analyzed in pairs in two steps using a 16-valued logic system, GEMINI. Forward propagation is performed to determine, for each line in the network, the set of all possible values it can take if the network contains any single or multiple faults. Based on the values observed at primary outputs, backward implication is performed to determine the value actually carried by each line. Some deduced values imply the line is not faulty; similarly, some values imply that there is a fault in the subnetwork driving the line, or on the line itself. By keeping track of this information, it is possible to locate a fault to within its equivalence class. An extended fault model which includes stuck-at, stuck-open, and delay faults is used. Multiple faults of all multiplicities are implicitly considered; thus, the results obtained using this method are not invalidated in the presence of untested or untestable lines.>

The problem considered is that of designing endfire line array shadings which provide a useful amount of supergain without extreme sensitivity to random errors. Optimum shading weights are obtained subject to a constraint on the gain against uncorrelated noise. The results of optimum array gain versus white noise gain constraint are presented parametrically for arrays of different inter-element spacings, and different noise fields. Results are presented for spherically and cylindrically isotropic noise and other wave-number limited noise fields, used in modeling ocean ambient noise. It is found that nearly optimum performance can be obtained in a simple delay and sum beamformer by shading to reduce sidelobes and modest oversteering to reduce main-lobe width without too large a reduction in main lobe sensitivity.