In this brief, a high-speed [multiway parallel (MWP)] hardware-implemented deflate data compressor (DDC) is proposed for reducing the storage of solid-state drives (SSDs). To minimize the area of the DDC, registers instead of static random access memories (SRAMs) are utilized for building hash tables because multiway data within the DDC are able to access a register-based hash table simultaneously. To further reduce the area of the DDC, the output data of indefinite length are concatenated with a tree-type hardware architecture for reducing the overall concatenation complexity. Moreover, a solid mathematical foundation is established for optimizing the latency values of Lempel–Ziv (LZ)77 circuit, the Huffman encoding circuit, and the output data concatenation circuit within the MWP DDC. The results show that the proposed MWP DDC is capable of achieving a 12.1-Gb/s throughput and a 1.76 compression ratio (CR) with a 1.17-mm2area and 0.103-$\mu $s latency, under the synthesis of SMIC 55-nm process design kits (PDKs). Hence, the proposed DDC satisfies the SSD compression requirement for a universal serial bus (USB) 3.2 connector.

In this brief, a high-speed secret merchant-4 (SM4) cryptographic circuit with strong robustness against differential power analysis (DPA) attacks is proposed for securing the wireless networks for the first time. To achieve a high-throughput design for the SM4 algorithm, 32-stage pipelined encryption rounds and key expansion rounds are employed. Moreover, to resist DPA attacks, one pseudorandom number generator (PRNG) is embedded to randomly alter the SM4 circuit with a 32-stage or 34-stage pipeline, the other PRNG is utilized for realizing redundant operations to further break the correlation between the processed data and power dissipation of the SM4 circuit. When compared to a regular SM4 cryptographic circuit, the proposed SM4 architecture is capable of achieving a high throughput and satisfactory robustness against DPA attacks without compromising much power, area, and performance overhead. The result shows that the pipelined SM4 cryptographic circuit achieves a 128-Gbps throughput and 47 423-$\mu$m$^2$area with a high measurement-to-disclosure (MTD) value ($>$1 million) after synthesizing in the SMIC 14-nm process design kits (PDKs).

Deep multi-view subspace clustering has achieved promising performance compared with other multi-view clustering. However, existing deep multi-view subspace clustering only considers the global structure for all views, and they ignore the local geometric structure among each view. In addition, they cannot learn discriminative feature on different clusters of different views, i.e., inter-cluster difference. To solve these problems, in this paper, we propose a novel Deep Multi-view Subspace Clustering with Unified and Discriminative Learning (DMSC-UDL). DMSC-UDL combines global and local structures with self-expression layer. The global and local structures help each other forward and achieve small distance between samples of the same cluster. To make samples in different clusters of different views farther, DMSC-UDL uses a discriminative constraint between different views. In this way, DMSC-UDL makes the same cluster's samples have large weights, while different clusters' samples have small weights. Thus, it can learn a better shared connection matrix for multi-view clustering. Extensive experimental results reveal that the proposed multi-view clustering method is superior to several state-of-the-art multi-view clustering methods in terms of performance.

Graph neural networks (GNNs) have made considerable achievements in processing graph-structured data. However, existing methods can not allocate learnable weights to different nodes in the neighborhood and lack of robustness on account of neglecting both node attributes and graph reconstruction. Moreover, most of multi-view GNNs mainly focus on the case of multiple graphs, while designing GNNs for solving graph-structured data of multi-view attributes is still under-explored. In this paper, we propose a novel Multi-View Attribute Graph Convolution Networks (MAGCN) model for the clustering task. MAGCN is designed with two-pathway encoders that map graph embedding features and learn the view-consistency information. Specifically, the first pathway develops multi-view attribute graph attention networks to reduce the noise/redundancy and learn the graph embedding features for each multi-view graph data. The second pathway develops consistent embedding encoders to capture the geometric relationship and probability distribution consistency among different views, which adaptively finds a consistent clustering embedding space for multi-view attributes. Experiments on three benchmark graph datasets show the superiority of our method compared with several state-of-the-art algorithms.