Cascading gain stages in CMOS Operational Transconductance Amplifiers (OTAs) has become a necessity in applications with high gain requirements, where the contribution of each stage to the overall gain is well-known and carefully designed. Many of these applications also impose requirements on speed, including a minimum Slew-Rate (SR) to ensure signal fidelity, however the impact of individual gain stages on the overallSRin multi-stage OTAs has been difficult to characterize–let alone carefully design. The difficulty arises due to the complexity of the compensation networks involved in these OTAs. This paper presents a systematic design approach for achieving a targetSRin multi-stage CMOS OTAs, enabled through the utility of a novel analytical model for estimating the lower-bound Slew-Rate in multi-stage OTAs. The model evaluates individual currents and equivalent capacitances at the output node of each stage, providing insights on the dominant node slowing down the overallSR. For generality, the model establishes theSRanalysis based on N-stage designs, and considers widely employed compensation networks. Example designs, with post-layout simulations and measurements of a 3- and a 4-stage CMOS OTA, and with post-layout simulations of a 5-stage CMOS OTA, are presented for validating the model’s utility. The results show strong agreement between theoretical, simulated, and measuredSRvalues, confirming the model’s reliability in estimating the lower-boundSR, and its utility in a systematic design-for-SRapproach in multi-stage CMOS OTAs.

This work introduces a multi-stage CMOS OTA design technique that allows cascading identical gain stages (for arbitrarily scalable high DC gain) while driving an ultra-wide range of capacitive loads ($\text{C}_{\text {L}}\text{s}$). At the heart of the proposed design is a new frequency compensation technique (FCT) that relies on low-frequency left-half-plane zeros to allow the proposed OTA to operate for a desired closed-loop behavior. In this work, classical gain-stages (i.e., differential pair and common source transistors) are used to design fully-differential 2-, 3-, 4- and 5-stage CMOS OTAs. The proposed 2-to-4-stage designs have been fabricated in TSMC 65 nm CMOS process and the measurement results show that the 2-stage OTA is achieving a DC gain of 50 dB with a$\text{C}_{\text {L}}$-drivability ratio (i.e.,$\text{C}_{\text {L,max}}/\text{C}_{\text {L,min}}$) of$10,000\times $, the 3-stage OTA is achieving a DC gain of 70 dB with a$\text{C}_{\text {L}}$-drivability of$1,000,000\times $, and the 4-stage OTA is achieving a DC gain of 90 dB with a$\text{C}_{\text {L}}$-drivability of$1,000,000\times $. This is a 10-to-1000-time improvement in the state-of-the-art, as the highest$\text{C}_{\text {L}}$-drivability reported to date is$1000\times $. Accordingly, the proposed OTAs can cover a wider range of applications than any other reported works.

This work introduces a new design technique for extending the load driving capability of conventional Miller-RC CMOS OTAs, up to nF-range capacitive loads (CL), with near-optimum small- and large-signal time responses. The proposed technique involves modifying the R-C compensation network such that the unity-gain frequency, æt, of the OTA is highly increased. This additional increase in ωtcan then be traded-off for higher loads by transferring the dependency of the dominant pole to CL. To implement and verify the proposed technique, the classical differential-ended two-stage OTA was used as a design example in order to drive a load of 1000 pF. Interestingly, with the modified compensation network, an area efficient design was achieved, demonstrating excellent performance.

In this work, a new scalable CMOS OTA design that systematically enables cascading many identical OTA stages is proposed. This scalable design of the many-stage OTA ensures stability, when configurated in closed loop, by means of a new scalable frequency compensation technique. The presented design realizes a CMOS OTA with scalable-gain that increases in 25 dB increments per stage, achieving a total gain from 50 dB to 150 dB for a 2-stage to a 6-stage OTA, respectively. Stability of the many-stage OTA is ensured by re-positioning the poles and zeros of all gain stages in a systematic scalable pattern whenever a new gain-stage is added. The presented design was based on a TSMC 65 nm CMOS process.

The presence of Pole-Zero (P-Z) pairs in the open-loop frequency response of CMOS OTAs has always been considered detrimental to the closed-loop operation of OTAs. In this work, a new proposed theory is presented showing how to reduce the impact of such P-Z pairs on the settling time of CMOS OTAs - using low-frequency zeros and cascaded-gain stages - consequently revealing un-tapped opportunities for many-stage CMOS OTA design. The proposed theory will be validated and verified through a design example that also demonstrates how the generalized theory unveils opportunities for many-stage OTA design. The presented example is a 2- to 8-stage CMOS OTA based on the TSMC 65 nm CMOS process, verified through simulations (schematic and post-layout) as well as some measurement results.