As the SRAM-based In-memory Computing (IMC) paradigm arises as a promising candidate to break the memory wall bottleneck and deliver optimal energy efficiency, reliability has been paid less attention. Serious reliability issues that concern a conventional SRAM cell includes increased process variations as well as the dominant transistor aging mechanisms, such as Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) phenomena. These degradation impacts the speed, noise margin and input offset voltage a SRAM structure. Though the vulnerability of a SRAM cell to transistor aging has been extensively studied in the literature, there is still missing information on how aging impacts the SRAM-based IMC architectures along with the process variability. In this work, through simulation, we present a comprehensive study on impact of aging and process variability on commonly employed SRAM-based 6T-and 8T-IMC architectures. In the current study, degradation’s stochastic behavior is examined by coupling process fluctuations brought on by aging. The confluences of two degradation mechanisms help to identify the worst-case failures. This study serves as one of the first ones that provide BTI induced aging analysis on multiple IMC logic operations and offer perspectives for designing robust SRAM-based IMC based architectures.