With growing concerns over physical security against power and electromagnetic side-channel attacks (SCA), this work provides a comprehensive analysis of different existing isolation countermeasures, especially the analysis of security-focused shunt low-dropout regulators (LDOs). Using both small-signal and large-signal analysis, we demonstrate that shunt LDOs offer superior security using the metric current-domain signature attenuation (CDSA) and load supply isolation (LSI) performance while mitigating mid-frequency power-supply ripple-rejection (PSR) peaking. Various existing shunt LDO architectures are evaluated, highlighting trade-offs between DC rejection and high-frequency CDSA response. Alternative isolation techniques such as galvanic isolation, digital LDOs, and integrated voltage regulators (IVRs) are also examined.

Recent expansions in multimedia devices for many applications, such as surveillance, self-driving cars, and healthcare, gather enormous amounts of real-time images for processing and inference. The images are first compressed using compression schemes, like joint photographics experts group (JPEG), before processing to reduce storage costs and additional power requirements for transmitting the captured data in this era of emerging ultra-wideband communication and human-body communication. The JPEG algorithm realizes image compression using simplistic matrix manipulations, making it preferable for hardware implementations. Furthermore, due to inherent error resilience and imperceptibility in images, JPEG can be approximated to reduce the required computation/processing power and area. This work demonstrates the first end-to-end approximation computing-based optimization of JPEG hardware using 1) an approximate division realized using bit-shift operators to reduce the complexity of the computationally intensive quantization block; 2) loop perforation; and 3) precision scaling on top of a multiplier-less fast discrete cosine transform (DCT) architecture to achieve an extremely energy-efficient JPEG compression unit which will be a perfect fit for power/bandwidth-limited scenario. Furthermore, a gradient descent-based heuristic composed of two conventional approximation strategies, i.e., precision scaling and loop perforation, is implemented for tuning the degree of approximation to tradeoff energy consumption with the quality degradation of the decoded image. The entire register-transfer level (RTL) design is coded in Verilog HDL, synthesized using the industry-standard tool, mapped to TSMC 65nm CMOS technology, and simulated using Cadence Spectre Simulator under 25 ° C, typical/typical (TT) corner. The approximate division approach in the quantization block achieved around 28% reduction in the active design area. The heuristic-based approximation technique combined with accelerator optimization achieves a significant energy reduction of 36% for a minimal image quality degradation of 2% sum of absolute difference (SAD). Simulation results also show that the proposed architecture consumes 15 uW at the DCT and quantization stages to compress a colored 480-p image at 6 frames/s.

Traditional deep learning models incur high computational overhead (approximately 1-30W) and are unsuitable for Ultra-Low-Power (ULP) wearable systems like smart glasses. In contrast, TinyML architectures are power-efficient but less accurate. We propose distributing a neural network (NN) between a ULP wearable node and a resource-rich hub to maintain high accuracy and low power consumption for applications like human-machine vision. Output features from the node are transmitted to the hub via low-power communication, where the remaining network runs on traditional GPUs. We introduce a Figure of Merit (FoM) to determine the optimal NN distribution point and a customized multiplier unit for ULP operation. Achieving ULP of 284μW and 9mW for different Autoencoder (AE) networks, our approach is 700× lower in power consumption compared to traditional GPU implementation.

Securing ICs are becoming increasingly challenging with rapid improvements in electromagnetic (EM) side-channel analysis (SCA) and fault injection (FI) attacks. In this work, we develop a pro-active approach to detect and counter these attacks by embedding a single on-chip integrated loop around a crypto core (AES-256), designed and fabricated using TSMC 65nm process. The measured results demonstrate that the proposed system 1) provides EM-Self-awareness by acting as an on-chip H-field sensor, detecting voltage/clock glitching fault-attacks; 2) senses an approaching EM probe to detect any incoming threat; and 3) can be used to induce EM noise to increase resilience against EM attacks. This work combines EM analysis, ML based secured system and shows the efficacy by measurements from custom-built 65nm CMOS IC.