Approximate arithmetic circuits sacrifice computing accuracy in exchange for improvements in power, area, and speed. Many approximate binary multipliers that use 4-2 compressors have been proposed but most of the proposals have error performances that depend on the order in which the inputs are connected to the compressors. This complicates the design and prevents a fair comparison among different approximate multipliers. The paper proposes the input order invariant approximate 4-2 compressors, whose behavior remains consistent regardless of the order of input signals. We derive the complete set of such compressors and utilize them to synthesize 8-bit multipliers. Our analysis reveals that only a limited subset of input order invariant approximate 4-2 compressors offers an optimal balance between error and power savings. Furthermore, we demonstrate that this optimal set of 4-2 compressors can be strategically distributed within the columns of the multiplier to further enhance the trade-off between error and power efficiency. The proposed circuits, once implemented in a 14 nm FinFET standard cell technology, favorably compare against the state of the art.

Error resilient applications benefit from the use of approximate computing techniques that enhance electrical performances while allowing a deviation from the exact result. Many operations in signal processing require the square of a signal. Despite the fact that the squaring operation can be regarded as a special multiplication case, it is often preferable to develop independent squaring circuits to exploit possible architectural symmetries. This paper proposes novel approximate binary squarers, obtained by recursively exploiting 4-bit approximate multipliers and squarers. The final designs cover a wide range of computing precision, providing the user with multiple choices of different cost vs. accuracy trade-offs. The proposed circuits, as well as competitive designs, are synthesized targeting a 14 nm FinFET technology to determine the electrical characteristics. It is demonstrated that the proposed squarers outperform the state-of-the-art in terms of power vs. precision. Compared to the exact 8-bit squarer, the least dissipative proposed design reduces silicon area by 76%, power consumption by 71%, and critical delay by 72%. The same circuit dissipates 2.4% less power than the least dissipative design found in literature, while providing 34% more accurate results. The behavior of the considered designs is also tested in common error resilient applications, like signal demodulation and image processing.

Digital Storage Oscilloscopes (DSOs) conjugate high performance with large number of features and flexibility. The basic structure, based on fast Analog to Digital Converter (ADC) and memory, is augmented with several components for channel matching and bandwidth improvement, and processors that provide visualization, frequency processing, jitter and stability measurement, etc. Unfortunately, fine resolution in sample rate selection is not available, such that for several applications the user must run complex measurement procedures that require data download and offline processing. The paper proposes a dedicated digital circuit that offers fine control of the time-base by real time downsampling the input stream at an almost arbitrary sampling rate. The proposed circuit implements a series of operations involving real-time data filtering, defragmentation and packing, which are not considered by alternative approaches, like those based on polyphase filters, that offer very limited choices for the sampling rate. The circuit is designed to work in conjunction with the highest performance DSOs that use a multichannel architecture. Design rules for circuit design are provided together with implementation results in 14nm FinFET technology. When designed for an architecture with 64 channels with 8bit input samples the circuit works in real time with a sampling rate of 220 GSps running at 3.42 GHz, with a silicon footprint of 0.17 mm2and a power dissipation of 0.85W.