Accurate prediction of temperature distributions is essential for safe and efficient battery pack design and management. In indirect liquid cooling configurations, battery cell layouts strongly influence internal heat transfer, which complicates layout-aware heat map prediction. However, existing data-driven and physics-informed surrogate models are often constrained by scarce high-fidelity data, grid-based discretizations, and insufficient generalization across varying layouts. To address these challenges, this paper proposes a physics-informed cross-attention operator network (PI-CAON), a mesh-free neural operator for steady-state heat map prediction in large-scale battery packs. The proposed model integrates Fourier feature encoding to represent multi-frequency thermal behaviors, a hard-constrained Fourier embedding to enforce Neumann boundary conditions, and a cross-attention-based feature fusion mechanism to explicitly capture inter-cell and layout-dependent thermal interactions. By embedding the governing heat transfer physics into training loss, PI-CAON enables label-free learning whilst maintaining physical consistency. Numerical experiments on a 20-cell indirect liquid cooling battery pack demonstrate that PI-CAON achieves accurate and robust heat map predictions across diverse layout configurations, with a maximum temperature error below 0.03 ° C . Comparative studies show that PI-CAON consistently outperforms grid-based methods, existing physics-informed neural operators, and purely data-driven baselines in both prediction accuracy and computational efficiency, highlighting its potential for battery thermal design optimization and uncertainty quantification.

Edge devices with limited resources are critical components of modern wireless communication systems. As communication environments become increasingly complex, neural networks are playing a larger role in processing large amounts of data to enable Machine Learning (ML) within these systems. While most FPGA-based accelerators focus on neural network inference, deploying the training phase on resource-constrained edge devices remains a significant challenge. Training on a System on Chip (SoC) that combines ARM processors with FPGA fabric provides unique benefits, including the ability to quickly adapt models to dynamic environments. This work leverages the Tiny Transfer Learning (TinyTL) framework for on-device training, which allows edge devices to continuously adapt neural network models to new data with minimal memory requirements. To the best of our knowledge, this is the first use of a heterogeneous platform to accelerate training using TinyTL. We present the Accelerating TinyTL-based Digital PreDistortion (ATDPD) system, designed to adapt to varying behaviors of power amplifiers in wireless communication systems and implement it on an AMD RFSoC. Our heterogeneous approach achieves comparable training accuracy to ARM-based systems, while accelerating the training phase by more than 20%.

The implementation of neural networks (NN) on edge devices enables local processing of wireless data but faces challenges such as high computational complexity and memory requirements when deep neural networks (DNN) are used. Shallow neural networks customized for specific problems are more efficient, requiring fewer resources, and resulting in a lower latency solution. An additional benefit of the smaller network size is that it is suitable for real-time processing on edge devices. The main concern with shallow neural networks is their accuracy performance compared to DNNs. In this paper, we demonstrate that a customized adaptive activation function (AAF) can meet the accuracy of a DNN. We designed an efficient FPGA implementation for a customized segmented spline curve neural network (SSCNN) structure to replace the traditional fixed activation function with an AAF. We compared our SSCNN with different neural network structures such as real-valued time delay neural network (RVTDNN), augmented real-valued time delay neural network (ARVTDNN), and deep neural networks with different parameters. Our proposed SSCNN implementation uses 40% fewer hardware resources and no Block RAMS compared to the DNN with similar accuracy. We experimentally validate this computationally efficient and memory-saving FPGA implementation of SSCNN for digital predistortion of RF power amplifiers using the AMD/Xilinx RFSoC ZCU111 while using less than 3% of the available resources, leaving space for additional real-time processing, while achieving the speed of 221 MHz.

Base stations in cellular networks must operate linearly, power efficiently, and with ever increasing flexibility. Recent FPGA hardware advances have demonstrated linearization using neural networks, however the latency introduced by these solutions is a concern. We present a novel hardware implementation for a low digital cost, high throughput pipelined Real Valued Time Delay Neural Network (RVTDNN) structure with a hardware-efficient activation function. Network training times are reduced by minimizing the training signal samples used, based on a biased probability density function (pdf). The design has been experimen-tally validated using an AMD/Xilinx RFSoC ZCU216 board and surpasses the data throughput of conventional RVTDNN-based DPD while using a fraction of their hardware utilization.

The recurrent recovery is one of the common methods for video super-resolution, which models the correlation between frames via hidden states. However, when we apply the structure to real-world scenarios, it leads to unsatisfactory artifacts. We found that, in the real-world video super-resolution training, the use of unknown and complex degradation can better simulate the degradation process of the real world. Based on this, we propose the RealFuVSR model, which simulates the real-world degradation and mitigates the artifacts caused by the video super-resolution. Specifically, we propose a multi-scale feature extraction module(MSF) which extracts and fuses features from multiple scales, it facilitates the elimination of hidden state artifacts. In order to improve the accuracy of hidden states alignment information, RealFuVSR use advanced optical flow-guided deformable convolution. Besides, cascaded residual upsampling module is used to eliminate the noise caused by the upsampling process. The experiment demonstrates that our RealFuVSR model can not only recover the high-quality video but also outperform the state-of-the-art RealBasicVSR and RealESRGAN models.