I/O performance has become a major bottleneck for many data-intensive applications. Each layer of the parallel I/O stack provides parameters that can optimize I/O performance, but determining the optimal performance parameters based on the operating configuration is a challenge. Previous work has required separate performance models for different programs for tuning, which is very costly in term of measurement data. We propose BLG-Tuning: a B enchmark-based L ow-cost G eneral-purpose I/O Modeling and Tuning. BLG-Tuning maps application I/O loads to benchmark parameters and uses the benchmark-trained performance model to achieve I/O performance prediction and thus avoid the additional computing and communication overhead for measurement. For applications, BLG-Tuning collects the application characteristics to calibrate the performance model and improve prediction accuracy. Experience shows that BLG-Tuning predicts the I/O time of MADbench2, Flash-IO, S3D-IO, BT-IO, and LAMMPS with MAPE of 22.2%, 18.2%, 29.3%, 21.5%, and 34.8%, respectively. After tuning, the five applications obtain I/O speedup from 5.6× to 27.3×.

Dynamic power consumption is a significant concern in modern integrated circuits. This issue is primarily caused by signal toggling, including unwanted toggles known as glitches. With the number of operations increasing in circuits, glitches can lead to significant additional dynamic power. This paper presents SMART-GPO, a novel framework that efficiently and accurately estimates and reduces glitch power. Our approach samples cycles for accurate glitch estimation, followed by gate-sizing and Vth assignment to optimize glitch power based on sensitivity measurements. We validated SMART-GPO on the Berkeley Out-of-Order Machine (BOOM) and Rocket SoCs with TSMC N28 technology. It achieves a mean absolute percentage error (MAPE) of 2% on glitch power estimation when running power analysis on only 1% simulation cycles. The optimization results demonstrate that our framework reduces glitch power by more than 9%, which outperforms previous approaches substantially.

Optical interconnects have emerged as a promising solution for rack-, board-scale, and even in-package communications, thanks to their high available optical bandwidth and minimal latency. However, the optical waveguides are intrinsically different from traditional metal wires, especially the phase matching constraints, which impose new challenges for routing in the photonic in-tegrated circuits design. In this paper, we propose a comprehensive and efficient optical routing framework that introduces a diffuse-based length-matching method and bend modification methods to ensure phase-matching constraints. Furthermore, we present a congestion-based A * formulation with a negotiated congestion-based rip-up and reroute strategy on new rectangular grids with an aspect ratio of 1:$\sqrt{3}$to reduce insertion loss. Experimental results based on real photonic integrated designs show that our optical routing flow can reduce total insertion loss by 11 % and maximum insertion loss by 108 %, while effectively satisfying matching constraints, compared to manual results.

While large language models (LLMs) have shown remarkable potential in automating various tasks in digital chip design, the field of Photonic Integrated Circuits (PICs)-a promising solution to advanced chip designs-remains relatively unexplored in this context. The design of PICs is time-consuming and prone to errors due to the extensive and repetitive nature of code involved in photonic chip design. In this paper, we introduce PICBench, the first benchmarking and evaluation framework specifically designed to automate PIC design generation using LLMs, where the generated output takes the form of a netlist. Our benchmark consists of dozens of meticulously crafted PIC design problems, spanning from fundamental device designs to more complex circuit-level designs. It automatically evaluates both the syntax and functionality of generated PIC designs by comparing simulation outputs with expert-written solutions, leveraging an open-source simulator. We evaluate a range of existing LLMs, while also conducting comparative tests on various prompt engineering techniques to enhance LLM performance in automated PIC design. The results reveal the challenges and potential of LLMs in the PIC design domain, offering insights into the key areas that require further research and development to optimize automation in this field. Our benchmark and evaluation code is available at https://github.com/PICDA/PICBench.

As silicon photonic integrated circuits (PICs) scale in density and integration level, thermal crosstalk significantly impacts chip performance and reliability, necessitating careful thermal-aware design. Traditional numerical solvers are prohibitively slow for large-scale 3D simulation, while existing machine learning surrogates struggle with generalization, especially under the complex distributed heaters and layered structures unique to PICs. We present ThermoPhoton, an operator-learning neural architecture tailored for efficient, accurate 3D thermal modeling of PICs. ThermoPhoton introduces a Pseudo-3D source representation (Pseudo-3D) that leverages device stratification, and applies Zero Coordinate Shift (ZCS) encoding to optimize physics-informed loss computation. Attention mechanisms further enhance the capture of sharp thermal gradients and crosstalk. On industry-standard benchmarks, ThermoPhoton achieves a mean absolute percentage error of 0.07%, reduces peak GPU memory by 67.1%, and shortens training time by 37.9% compared to prior operator-based methods, enabling fast, reliable, and scalable thermal analysis for next-generation photonic chips.

Photonic integrated circuits (PICs) have emerged as a promising solution for next-generation computing and interconnects, delivering enhanced performance in bandwidth and energy efficiency compared to conventional electronics. Previous studies on automatic optical routing have typically assumed uniform waveguide classes, neglecting the real-world requirement for multiple waveguide types to enhance performance and integration density. To address this gap, we propose an adaptive waveguide routing framework explicitly tailored for PICs that effectively handles hybrid waveguide classes. Our method starts with a fast initial routing algorithm that optimizes waveguide paths, considering target net lengths or length matching constraints among nets, minimizing bends, and ensuring compatibility with hybrid waveguide usage. We further enhance routing quality using a mixed integer linear programming (MILP)-based automatic transition insertion technique, strategically employing different waveguide types to significantly reduce transmission loss and ensure compliance with stringent matching constraints. Experimental results show that, compared to prior approaches, our algorithm reduces total insertion loss by up to 37% on average in target-length routing scenarios, and achieves an average reduction of 5% in total insertion loss and 14% in maximum loss in multi-net cases while satisfying all constraints.