Abstract Network-on-Chip (NoC) is a promising technology that uses a network of interconnected processing elements to improve performance and reduce communication costs in complex systems. However, faults can occur in NoC systems due to various factors such as manufacturing defects, aging, and environmental factors. To address this challenge, fault-tolerant techniques are necessary to ensure the reliable and efficient operation of NoC systems. One such technique is fault-tolerant application mapping, in which application cores are assigned to processing elements to reduce the system performance degradation caused by the failures. However, the application mapping for NoC systems, including fault tolerance, is a complex task. This paper presents a novel approach consisting of a transformer-based reinforcement learning algorithm for application mapping in mesh topology based NoC. This allows NoC to communicate efficiently in the presence of faults. The proposed approach is compared with other state-of-the-art techniques. The findings demonstrate that the proposed approach outperforms the average communication cost encompassing 2, 5, and 7 percent more than RL-MAP, NMA, and PSO, respectively, and also has less run-time. Also, it is observed that the introduced technique excels against the remaining techniques with respect to the average network latency decrease by 3, 5, and 6 percent for RL-MAP, NMA, and PSO correspondingly. The approach in this method is thus helpful in the design of NoC systems that are energy efficient as well as reliable for targeted applications.

This paper explores the enhancement of convolutional image processing on a RISC-V based architecture through the implementation of branch prediction (BP) techniques. Con-volution, a critical operation in image processing, is essential for tasks such as edge detection, blurring, and feature extraction. Efficient execution of convolution operations, particularly in a RISC-V architecture, requires effective BP to minimize delays caused by conditional operations. This study presents the development of a 5-stage pipelined 32-bit RISC-V processor, integrated with a 2-bit saturating counter branch predictor using a Branch History Table (BHT). The efficiency of the RISC-V processor was evaluated by synthesizing and implementing it using Xilinx Vivado on the Kintex- 7 KC705 Evaluation Platform and testing with a convolution algorithm written in assembly language. Experimental results demonstrate that optimizing BP significantly improves the execution efficiency of convolution operations, making it a promising approach for advanced image processing applications.

Network-on-Chip (NoC) is a communication paradigm that has increased in popularity as a solution for intra-chip communication in complex System-on-Chip (SoC) designs, as it avoids complex interconnects. The functional verification of the NoC is a crucial step in the design life-cycle of a NoC based SoC, as it directly impacts the SoC behavior and latency. Automation of the NoC functional verification process could greatly improve the time-to-market of such complex SoC designs. One such approach to automation is the use of Genetic Algorithm to generate NoC traffic such that it achieves maximum functional coverage in less simulation time.

Application mapping is one of the early stage design processes aimed to improve the performance of Network-on-Chip. Mapping is an NP-hard problem. A massive amount of high-quality supervised data is required to solve the application mapping problem using traditional neural networks. In this article, a reinforcement learning–based neural framework is proposed to learn the heuristics of the application mapping problem. The proposed reinforcement learning–based mapping algorithm (RL-MAP) has actor and critic networks. The actor is a policy network, which provides mapping sequences. The critic network estimates the communication cost of these mapping sequences. The actor network updates the policy distribution in the direction suggested by the critic. The proposed RL-MAP is trained with unsupervised data to predict the permutations of the cores to minimize the overall communication cost. Further, the solutions are improved using the 2-opt local search algorithm. The performance of RL-MAP is compared with a few well-known heuristic algorithms, the Neural Mapping Algorithm (NMA) and message-passing neural network-pointer network-based genetic algorithm (MPN-GA). Results show that the communication cost and runtime of the RL-MAP improved considerably in comparison with the heuristic algorithms. The communication cost of the solutions generated by RL-MAP is nearly equal to MPN-GA and improved by 4.2% over NMA, while consuming less runtime.

With the increasing number of applications running on a Network-on-Chip (NoC) based System-on-Chip (SoC), there is a need for designing a reconfigurable NoC platform to achieve acceptable performance for all the applications. This paper proposes a novel architecture for implementing a reconfiguration logic to the NoC platform executing multiple applications. The proposed architecture reconfigures SoC modules to the routers in the NoC with the help of tri-state buffers based on the applications running. The overhead in implementing the reconfiguration circuitry is significantly less, approximately 0.9% of the area and 1% of the total power consumed by the router network. The architectures presented in the paper are developed in Verilog HDL, applied to the NoC router platform and simulated for functional verification. The synthesis results show that the proposed tri-state buffer-based reconfiguration logic has better performance in terms of area, power and speed compared with the multiplexer-based reconfiguration logic.

In the nano-scale era, to improve the system reliability the major challenge is to predict the NoC component failures in runtime and propose an efficient technique. To predict the failures in runtime, probabilistic based models have been proposed in the literature. However, these techniques provide an empirical model to predict failure. Hence, there is a need for the dynamic fault-model that predicts the runtime failures in NoC design. This paper presents a novel fault-model for the interconnection links in application-specific Network-on-Chip (NoC) design. The proposed model acts as a baseline reference to predict the faults during the runtime of an application on NoC. The experimentations have been carried for different widths of the interconnection links by providing application-specific traffic patterns. The results show that the meantime to failure of an interconnection links having width of 0.3 μm, and 1 μm getting reduced with increase in the link bandwidth.

As the technology is scaling down more number of processing elements are integrated on to a single chip, namely system-on-chips (SoCs). Using traditional bus architecture in SoCs, communication among different processing elements is difficult. Hence, to overcome it, a new on-chip interconnection paradigm known as network-on-chip (NoC) has been proposed. The communication among different processing elements in NoCs is achieved using packet switching technique. In nano-scale era, NoCs are prone to vulnerable faults and designing an NoC to meet current application requirements is highly challenging. Hence, there is a need to develop reliable and efficient Fault-tolerant NoC designs. This paper presents a novel Fault-Tolerant NoC design for butterfly-fat-tree (BFT) topology with flexible spare core placement by taking different benchmark applications into consideration. The major challenge in fault-tolerant NoC is placement of spare core in the event of core failure in BFT network. Therefore, we have proposed an integer linear programming (ILP)-based exact method and particle swarm optimisation (PSO)-based meta-heuristic technique to place the spare core in a BFT network. Our major contribution is to place the spare core in BFT network such that system performance is improved in terms of communication cost, network latency, and router power consumption. Experimentations have been performed on several application benchmarks reported in the literature, (i) by varying the network size with fixed fault-percentage in the network, (ii) by varying the percentage of faults while fixing the network size and (iii) by taking multiple failed cores as a user input. We have compared overall communication cost obtained using our approaches with native fault-free approach. We have also compared overall communication cost and CPU runtime between ILP and PSO. The results show improvement in terms of overall communication cost, average network latency and network power consumption using our approaches compared to fault-free approach in BFT networks.

Network-on-Chip (NoC) has been proposed as a promising solution to overcome the communication challenges of System-on-Chip (SoC) design in nanoscale technologies. With the advancement in the nanoscale technology, the integration density of Intellectual Property (IP) cores in a single chip have increased, leading to heat dissipation, which in turn makes the system unreliable. Therefore, efficient fault-tolerant methods are necessary at different levels to improve overall system performance and make the system to operate normally. This article presents a flexible spare core placement technique for mesh-based NoC by taking several benchmark applications into consideration. An Integer Linear Programming (ILP)-based solution has been proposed for the spare core placement problem. Also, Particle Swarm Optimisation (PSO)-based meta-heuristic has been proposed for the same. Experiments have been performed by taking several application benchmarks reported in the literature and the applications generated using the TGFF tool. Comparisons have been carried out using our approach and the approach followed in the literature (i) by varying the network size with fixed fault percentage in the network, and (ii) by fixing the network size while varying the percentage of faults in the network. We have also compared the overall communication cost and CPU runtime between ILP and PSO approaches. The results show significant reductions in the overall communication cost, average network latency, and network power consumption across all the cases using our approach over the approaches reported in the literature.

As the size of the chip is scaling down the density of Intellectual Property (IP) cores integrated on a chip has been increased rapidly. The communication between these IP cores on a chip is highly challenging. To overcome this issue, Network-on-Chip (NoC) has been proposed to provide an efficient and a scalable communication architecture. In the deep sub-micron level NoCs are prone to faults which can occur in any component of NoC. To build a reliable and robust systems, it is necessary to apply efficient fault-tolerant techniques. In this paper, we present a flexible spare core placement in Mesh-of-Tree (MoT) topology using Particle Swarm Optimization (PSO) by considering IP core failures in NoC. We have experimented by considering several application benchmarks reported in the literature. Comparisons have been carried out, (i) by varying the percentage of faults in the MoT network with fixed network size and (ii) by considering the each core has been failed in the given application benchmark. The results show limited overhead in communication cost while providing fault-tolerance.

Due to the increase in the number of processing elements in System-on-Chips (SoCs), communication between the cores is becoming complex. A solution to this issue in SoCs gave rise to a new paradigm called Network-on-Chips (NoCs). In NoCs, communication between different cores is achieved using packet based switching techniques. In the deep sub-micron technology, NoCs are more susceptible to different kinds of faults which can be transient, intermittent and permanent. These faults can occur at any component of NoCs. This paper presents a novel Fault-Tolerant Routing (FTR) technique for Mesh-of-Tree (MoT) topology in the presence of router faults. The proposed technique is compared with routing technique without any faults. The results show improvements interms of the number of data packets reaching to any given destination node from any source node in MoT network in presence of faults.

The addition of express channels to a traditional mesh network-on-chip (NoC) has emerged as a viable solution to solve the problem of high latency. In this article, we address the problem of integrated mapping and synthesis for express channel--based mesh NoC topologies. An integer linear programming--based formulation has been presented for the mapping problem followed by a constructive heuristic for simultaneous application mapping and synthesis for an express channel--based NoC. The static and dynamic simulation results indicate that the obtained mappings lead to significant reduction in both average packet delay and network energy consumption. The obtained synthesized topologies were also found to be much more power efficient compared to conventional express channel topologies.

This article proposes a reconfigurable Network-on-Chip (NoC) architecture based on mesh topology. It provides a local reconfiguration of cores to connect to any of the neighboring routers, depending upon the currently executing application. The area overhead for this local reconfiguration has been shown to be very small. We have also presented the strategy to map the cores of an application set onto this architecture. This has been achieved via a two-phase procedure. In the first phase, the cores of the combined application set are mapped tentatively to individual routers, minimizing the communication cost. In the second phase, for each application, positions of individual cores are finalized. A core gets attached to any neighbor of its tentative allocation. We have proposed Integer Linear Programming (ILP) formulation of both the phases. Since ILP takes large amount of CPU time, we have also formulated a Particle Swarm Optimization (PSO)-based solution for the two phases. A heuristic approach has also been developed for the reconfiguration. Comparison of communication cost, latency and network energy have been carried out for the applications, before and after reconfiguration. It shows significant improvement in performance via reconfiguration.