Spiking neural network models when deployed in dynamic environments, catastrophically forget previously learned tasks. In this paper, we propose a reconfigurable spiking digital accelerator, which uses activity-dependent metaplasticity to mitigate catastrophic forgetting. The proposed accelerator has a custom low precision dual fixed point representation for network parameters. The custom precision leads to lower quantization error and higher accuracy. We evaluate the proposed accelerator on split-MNIST continual learning benchmark. Analysis shows that representing network parameters with 8-bit dual fixed point numbers reduces the memory footprint compared to 16-bit fixed point numbers, while maintaining comparable continual learning ability.

Metaplasticity, the activity-dependent modification of synaptic plasticity, is an important technique for mitigating catastrophic forgetting in neural networks. Often, continual learning models with metaplasticity require compute-intensive training. In this research, we propose a probabilistic metaplastic synapse with discrete hidden states that alleviates the computational cost. We implement a digital architecture of the network with on-chip training to achieve further power savings. Results show upto ~ 22% and ~ 21% improvement in mean accuracy for Split-MNIST and sequential MNIST-FMNIST benchmarks respectively, compared to previous metaplasticity models. Simulations of the full digital architecture show ~ 53× lower power consumption per weight update with similar accuracy as gradient-based network counterparts.

Recent studies have shown that metaplastic synapses can retain information longer than simple binary synapses and are beneficial for continual learning. In this paper, we explore the multistate metaplastic synapse characteristics in the context of high retention and reception of information. Inherent behavior of a memristor emulating the multistate synapse is employed to capture the metaplastic behavior. An integrated neural network study for learning and memory retention is performed by integrating the synapse in a 5 × 3 crossbar at the circuit level and 128 × 128 network at the architectural level. An on-device training circuitry ensures the dynamic learning in the network. In the 128 × 128 network, it is observed that the number of input patterns the multistate synapse can classify is ≃ 2.1× that of a simple binary synapse model, at a mean accuracy of ≥ 75%.