Recent advancements in transistor scaling have intensified reliability concerns in semiconductor devices. Addressing these issues requires a thorough understanding of the electrical properties of resources within the chip. This paper presents ManAge, a tool tailored for FPGA characterization with sub-picosecond timing resolution. ManAge offers an automated workflow spanning from generating test schemes to FPGA testing and data processing.

High-resolution phase shifters have important practical applications in PET scanners, time-to-digital converters, and characterizing of the FPGA resources. This paper presents a fine-grained clock phase-shifting technique based on the FPGAs' clock managers' dynamic phase shifting capability that is commonly available on all recent FPGAs. Our method allows adjusting the phase shift resolution in the sub-picosecond range independent of the operating frequency. Experiments carried out on a Xilinx UltraScale+ FPGA show that phase-shifting resolution can be adjusted down to 88 f s in these devices. To verify the performance of this method, we have deployed it in a delay characterization circuit to measure the FPGA's resources delays. The experiments show that we can measure path delays below 1 ns which is impossible in conventional frequency sweep-based methods and we reach a much finer time resolution.

The deployment of FPGAs in cloud data centers has entailed new security concerns. Although several defensive mechanisms are employed to detect and prevent malicious designs, a health monitoring tool can warn cloud service providers about the failure of implemented defensive fences. This PhD project aims to monitor the health status of internal FPGA resources by performing a precise timing characterization.