As the safety-critical applications (e.g., automotive and medical electronics) emerge, various techniques of radiation hardening by design (RHBD) are proposed to deal with soft errors. Among all RHBD techniques, Built-In Soft-Error Resilience (BISER) is the first one to apply the delayed latching to separate input signals on all flip-flops for error detection. However, the delay values induced by BISER extend the setup time of all flip-flops, and may fail to meet the timing specification of the design. For minimizing such delay impact on the setup time of each flip-flop, we propose the Automated Latching-Delay Assignment (ALDA) to transfer partial values to the CK-Q delay. Later, Time-Borrowable D-Flip-Flop (TBD-FF) as well as a modified design flow is also proposed to realize the delay assignment by ALDA and to complete the design hardening. Experiments show that ALDA together with TBD-FF effectively protects five benchmark circuits against soft errors, and optimally avoids the timing violations caused by the prior delayed-latching solutions.

Among various radiation hardening by de-signs (RHBD), triple-modular redundancy (TMR) is frequently used to correct soft errors. One of the well-known TMR solutions is called $\Delta{\mathrm TMR}$, which makes three copies of flop-flops (FFs) and inserts different delay buffers in front of data inputs of the second and third FFs for capturing soft errors. However, such solution has shortcomings in the area/power overhead and the imbalanced rise/fall delay. As a result, a novel TMR flip-flop design called area-minimized soft-error-recoverable flip-flop (AMSER-FF) is proposed in this paper to reduce the area/power overhead and timing degradation. Each AMSER-FF embeds a reference voltage generator (RVG), which generates balanced rise/fall delay and has fixed area utilization instead of inserting delay buffers for correcting errors. Experimental results show that AMSER-FF achieves lower area overhead, power overhead and less timing degradation than $\Delta\mathrm{TMR}$.

As the demand of safety-critical applications (e.g., automobile electronics) increases, various radiation-hardened flip-flops are proposed for enhancing design reliability. Among all flip-flops, Delay-Adjustable D-Flip-Flop (DAD-FF) is specialized in arbitrarily adjusting delay in the design to tolerate soft errors induced by different energy levels. However, due to a lack of testability on DAD-FF, its soft-error tolerability is not yet verified, leading to uncertain design reliability. Therefore, this work proposes Delay-Adjustable, Self-Testable Flip-Flop (DAST-FF), built on top of DAD-FF with two extra MUXs (one for scan test and the other for latching-delay verification) to achieve both soft-error tolerability and testability. Meanwhile, a built-in self-test method is also developed on DAST-FFs to verify the cumulative latching delay before operation. The experimental result shows that for a design with 8,802 DAST-FFs, the built-in self-test method only takes 946 ns to ensure the soft-error tolerability. As to the testability, the enhanced scan capability can be enabled by inserting one extra transmission gate into DAST-FF with only 4.5 area overhead.

In modern VLSI design flow, timing analysis is crucial for verifying whether a circuit design can operate without errors. Soft-delay effect (SDE), which is a kind of degraded soft error, will make system failed though the circuit has passed the typical timing analysis. Therefore, we propose a soft-delay-aware timing analysis which takes SDE into consideration. Additionally, a path-fixing mechanism is also proposed to fix up the violated paths automatically. Experimental results show that only 1.05% area budget is required averagely that all violated paths can be fixed up. In summary, SDPTA and the path-fixing mechanism are capable of reducing SDE to general circuits without other manual effort.

For the safety-critical applications such as biomedical and automobile electronics, the system failure induced by soft errors becomes a major issue of reliability. However, most of the commercial cell libraries do not include radiation-hardened components to build a safety-critical design. Therefore, a delay-adjustable D-flip-flop (DAD-FF) is proposed together with a design flow to construct a radiation-hardened system by automation. To enable such radiation-hardened design into the current design flow, DAD-FF is characterized as a general cell and compiled as a patch in the NanGate FreePDK45 bulk 45-nm open cell library, as an example. The experimental results show that DAD-FF is capable of reducing 1.3 × 1010X soft errors with respect to the standard flip-flop (STD-FF) and resisting over 99.999997% strikes of heavy ions. Meanwhile, four radiation-hardened benchmark circuits are synthesized with DAD-FF cell, and further used to prove the effectiveness against soft errors compared to a prior work, built-in soft-error resilience (BISER), with 18% area and 40% timing improvement. To sum up, DADFF is elaborated from the modeling at the device-level to the validation at the system-level and exhibits its strong robustness to soft errors.