Pseudo-Exhaustive Physically-Aware Region (PEPR) testing, in its most general application, rasterizes the layout of a logic circuit into overlapping three-dimensional regions of user-defined size. Faults that correspond to the exhaustive testing of each subcircuit within a region are defined and used for automatic test pattern generation (ATPG), fault simulation, and diagnosis. Evaluation of tens of thousands of chip failures demonstrated the effectiveness of PEPR in capturing the exact behavior of defects.However, deployment of PEPR is challenged by the large number of faults produced for exhaustively testing each region. Analysis revealed that there are a small percentage of regions that require a significant number of faults. For instance, a 14nm test chip contains regions that require more than 32M faults to test. While it is certainly possible to define a region size that produces large subcircuits, we found that large subcircuits predominantly result from including the entirety of a cell when a region simply intersects a small portion of the cell. To remedy this situation, we have developed IC-PEPR, a novel intra-cell extension to PEPR that significantly reduces the number of resulting faults. Specifically, by exploiting equivalence within a cell, intra-cell components within a region are controlled to all possible values without applying all cell-level input patterns. Applying IC-PEPR testing reduces the number of faults for a commercial benchmark circuit by more than 100X. This reduction in fault count results in a corresponding reduction in ATPG run time (almost 50X reduction) and test set size (>10X reduction).

Logic circuit diagnosis is an essential tool for improving manufacturing yield. However, there is a significant disparity between the behavior predicted by conventional fault models and the actual behavior observed in failing circuits. This undermines the performance of diagnosis methodologies that rely on conventional fault models to characterize defect behavior. Recently, a parameterizable test metric called PEPR has demonstrated the ability to precisely bound defect behavior, even when it deviates from conventional fault model assumptions. This paper describes a novel diagnosis methodology that uses the PEPR metric to determine (i) the physical location of a defect and (ii) the precise changes to the logic functionality of the affected circuit in the form of a custom fault model. The methodology, called CHEF, is applied to over 700 fail logs from a 22nm industrial test chip. Results demonstrate CHEF precisely characterizes defects that conventional diagnosis cannot, specifically when failure behavior does not align with a conventional fault model. Furthermore, CHEF achieves a significant increase in diagnostic resolution compared to conventional diagnosis, more than doubling the number of failures with a physical resolution better than 1µm2. Finally, diagnostic patterns generated by CHEF demonstrate the capability to further refine defect characterization.

Recently, companies such as Google, Meta (Facebook), and Microsoft reported in the mainstream press about seemingly random errors which, initially undetected ("silently"), had crept into their large cloud data centers. These reports mentioned that very specific instructions were intermittently incorrectly executed, propagated through the operating system, and would potentially manifest themselves as application-level errors. Are the root causes of these so-called silent data errors test escapes and/or reliability issues? Why are they only noticed now? Is that only the case because such large server farms bring together larger numbers of CPUs than ever seen before? And what counter measures can we take against them?

It is well-known that understanding the behavior of silicon failures is an essential step in yield learning. It is also becoming more important for producing high-quality silicon due to the increasing number of defects detected fortuitously. In order to meet this need, a new approach for extracting the precise faulty function from defective logic circuits is described. The approach is applied to nearly a 1,000 14nm failures and one use case of the results on improving ATPG is discussed.

Neuromorphic architectures have been introduced as platforms for energy-efficient spiking neural network execution. The massive parallelism offered by these architectures has also triggered interest from nonmachine learning application domains. In order to lift the barriers to entry for hardware designers and application developers, we present RANC: a reconfigurable architecture for neuromorphic computing, an opensource highly flexible ecosystem that enables rapid experimentation with neuromorphic architectures in both software via C++ simulation and hardware via FPGA emulation. We present the utility of the RANC ecosystem by showing its ability to recreate behavior of IBM’s TrueNorth and validate with a direct comparison to IBM’s Compass simulation environment and published literature. RANC allows optimizing architectures based on application insights as well as prototyping future neuromorphic architectures that can support new classes of applications entirely. We demonstrate the highly parameterized and configurable nature of RANC by studying the impact of architectural changes on improving application mapping efficiency with quantitative analysis based on Alveo U250 FPGA. We present post routing resource usage and throughput analysis across implementations of synthetic aperture radar classification and vector matrix multiplication applications, and demonstrate a neuromorphic architecture that scales to emulating 259K distinct neurons and 73.3M distinct synapses.