Digital transformation improves the operational efficiency and perceptual capabilities of businesses and creates a foundation for fulfilling ESG responsibilities. The authors use the theories of technological innovation and dynamic capabilities and select a sample of 4054 listed companies with commercial integration of ESG rating data to explore the mechanisms through which digital transformation affects ESG performance. Dynamic capabilities are further divided into innovation changeability (IT), coordination integration capability (CI), and learning absorption capability (LA) to investigate the mediating effects and summarize the causal path of “digital transformation - dynamic capabilities - ESG performance.” The research focuses on the impact of digital technology on ESG performance with the aim of helping businesses utilize technology more effectively to build dual competitive advantages in digitization and ESG.

Knowledge tracing focuses on modeling learners' past answer sequences to trace the evolving knowledge state and predict their performance in the future. Most of the existing GNN-based knowledge tracing model only considers the static pairwise relationship between concepts and exercises, but ignores the mining of edge features. Also, the dynamic and complex higher-order relationships hidden in the learners' answer sequence have not been fully exploited. In this paper, a novel hypergraph-based knowledge tracing model (HGKT) is proposed to address these limitations. Firstly, we exploit edge feature that indicates the frequency of exercise-concept's occurrence to extend the common bipartite graph. Then we use Node and Edge features based graph Neural Networks (NENN) to obtain the embedding representation of exercises and concepts. Secondly, a hypergraph with different weights on vertices is constructed during the learners' exercise-answering process and then it is transformed to a simple graph based on its similarity between hyperedges. Thereafter, we use the hypergraph neural networks (HGNN) and line hypergraph convolution network (LHCN) to obtain the learners' embedding and discover the higher-order relationships formed during this process. Thirdly, the difficulty of exercises and the average response time are utilized to improve the learning of LSTM's hidden states. Finally, all the embeddings are jointly added to the generalized interaction module of GIKT to draw attention to the useful information for prediction. Experiments demonstrate that the proposed HGKT outperforms previous classical methods in terms of AUC on the three widely used datasets.

As customized accelerator design has become increasingly popular to keep up with the demand for high performance computing, it poses challenges for modern simulator design to adapt to such a large variety of accelerators. Existing simulators tend to two extremes: low-level and general approaches, such as RTL simulation, that can model any hardware but require substantial effort and long execution times; and higher-level application-specific models that can be much faster and easier to use but require one-off engineering effort.This work proposes a compiler-driven simulation workflow that can model configurable hardware accelerator. The key idea is to separate structure representation from simulation by developing an intermediate language that can flexibly represent a wide variety of hardware constructs. We design the Event Queue (EQueue) dialect of MLIR, a dialect that can model arbitrary hardware accelerators with explicit data movement and distributed event-based control; we also implement a generic simulation engine to model EQueue programs with hybrid MLIR dialects representing different abstraction levels. We demonstrate two case studies of EQueue-implemented accelerators: the systolic array of convolution and SIMD processors in a modern FPGA. In the former we show EQueue simulation is as accurate as a state-of-the-art simulator, while offering higher extensibility and lower iteration cost via compiler passes. In the latter we demonstrate our simulation flow can guide designer efficiently improve their design using visualizable simulation outputs.

Field-programmable gate arrays (FPGAs) provide an opportunity to co-design applications with hardware accelerators, yet they remain difficult to program. High-level synthesis (HLS) tools promise to raise the level of abstraction by compiling C or C++ to accelerator designs. Repurposing legacy software languages, however, requires complex heuristics to map imperative code onto hardware structures. We find that the black-box heuristics in HLS can be unpredictable: changing parameters in the program that should improve performance can counterintuitively yield slower and larger designs. This paper proposes a type system that restricts HLS to programs that can predictably compile to hardware accelerators. The key idea is to model consumable hardware resources with a time-sensitive affine type system that prevents simultaneous uses of the same hardware structure. We implement the type system in Dahlia, a language that compiles to HLS C++, and show that it can reduce the size of HLS parameter spaces while accepting Pareto-optimal designs.