This paper presents an analysis of the application of an intentionally mismatched capacitive Digital-to-Analog Converter (CDAC) to improve the area efficiency and accuracy of successive-approximation register (SAR) analog-to-digital converters. The proposed SAR ADC architecture, the redundant capacitor-saver SAR ADC, utilizes 1-bit redundancy with intentional mismatch to estimate an additional resolution bit. This redundancy bit not only enhances noise tolerance but also achieves higher resolution through area- and energy-efficient computations, without requiring the addition of non-ideal, area-consuming, and energy-intensive capacitors to the CDAC block of the conventional SAR ADC. Simulations were conducted using Cadence TSMC 130nm CMOS technology and MATLAB software for conventional, redundant, and redundant capacitor-saver SAR ADCs, demonstrating 3 dB and 2 dB improvements in SNDR and SFDR, respectively, when using the capacitor-saver DAC architecture.

This paper conducts a detailed analysis of the impact of channel charge injection on the capacitive digital-to-analog (DAC) block in successive-approximation register (SAR) analog-to-digital converters (ADCs). It introduces a CAD tool for distinguishing various non-idealities, quantifying channel charge injection across all possible binary output codes. It enables the implementation of more effective compensation methods rather than relying on simple dummy switches by detecting most effective switches. All simulations are conducted using Cadence TSMC 130nm CMOS technology and MATLAB software, implying on 5 to 7 dB degradation in SNDR when considering the effect of channel charge injection in 6, 9, and 12-bit typical SAR ADCs.

This paper presents a hybrid pipeline SAR ADC with a loop-unrolled structure to reduce the crossbar’s ADC power while maintaining high speed. The 1ststage memristive SAR ADC can fully utilize the TIA originally in the crossbar and avoid the extra MDAC in pipeline ADC. Further, memristive weight calibration and a new resistive alternated binary search are implemented on the 1ststage to maintain the TIA gain and ADC’s accuracy. Both stage’s ADC are loop-unroll to eliminate the delay brought by SAR logic for high speed. Through multiple simulations, the design is demonstrated to be robust to the frequency and mismatch variations with the highest sampling frequency reaching 300MHz and SNDR up to 65.1dB in 9MHz input. The power consumption is designed to be as low as 6.7mW, which helps the ADC to achieve a 15.2fJ/conv FoM. Not limited to the crossbar, the presented ADC also shows promising potential for applications in various fields (biomedical, IoT etc.) for general purposes.