DRAM latency remains a critical bottleneck in the performance of modern computing systems. However, the latency is excessively conservative due to the timing margins imposed by DRAM vendors to accommodate rare worst-case scenarios, such as weak cells and high temperatures. In this study, we introduce a temperature- and process-variation-aware timing detection and adaptation DRAM (TPDA-DRAM) architecture that dynamically mitigates timing margins at runtime. TPDA-DRAM leverages innovativein-situcross-coupled detectors to monitor voltage differences between bitline pairs inside DRAM arrays, ensuring precise detection of timing margins. Additionally, the proposed detector inherently accelerates the precharge operation of DRAM, thereby reducing the precharge latency by up to 62.5%. Building upon this architecture, we propose two variation-aware timing adaptation schemes: 1) a process-variation-aware adaptation (PVA) scheme that accelerates access to weak cells, mitigating process-induced timing margins, and 2) a temperature-variation-aware adaptation (TVA) scheme that leverages temperature information and the restoration truncation technique to reduce DRAM latency, mitigating temperature-induced timing margins. Evaluations on an eight-core computing system show that TPDA-DRAM improves average performance by 21.8% and energy efficiency by 18.2%.

Charge-recycling bus (CRB) achieves quadratic energy savings by stacking two data channels between VDD and VSS. However, it suffers from middle voltage (VMID) drift due to unbalanced data activities of the two channels, which increases signal propagation delay and causes timing violations. In this paper, we present ASF-CRB, a CRB architecture that addresses the VMID drift problem at minimum energy costs based on a novel data transmission scheme named Alternate Signal Flipping (ASF). By reconfiguring the signal transmission path every cycle through a multiplexer at each pipeline stage, ASF ensures all bits flip once in every two pipeline stages. This averages each channel's high and low activities to 50% and thus contributes to balanced data activities between stacked channels. Lightweight latch structures tailored to CRBs are presented to minimize the delay and energy overheads, and a complete ASF-CRB architecture is developed for applicability in VLSI systems. The proposed ASF-CRB is implemented at a 28nm CMOS process. Post-layout simulations show that ASF-CRB achieves up to 41.0% energy saving at similar VMID stability and ∼2.7× smaller VMID drifts at similar energy consumption compared with the state-of-the-art CRB structure.

By stacking two data channels between VDD and VSS, Charge Recycling Buses (CRBs) halve the voltage swing on interconnects, achieving significant power savings for energy-efficient on-chip data transmission. However, the middle voltage (VMID) between the two channels may fluctuate dynamically due to the diversity of input data, which significantly impacts data propagation delay and reliability. Unfortunately, existing SPICE-based simulators do not run fast enough to identify the worst-case VMID fluctuation and propagation delay, posing great challenges in CRB design. In this paper, we present a dedicated CRB Simulator for fast and accurate VMID and timing analysis. A highly condensed VMID fluctuation model, which integrates each cycles VMID changes into a single closed-form formula, is embedded in the simulator to predict VMID values at clock edges. In addition, a speed-monitoring algorithm is developed to track the continuously changing signal propagation speed under intra-cycle VMID fluctuations for accurate delay estimation. Both the VMID fluctuation model and the delay estimation algorithm involve only a small number of arithmetic operations, thus featuring remarkably low computational complexity. Compared with HSPICE, our CRB Simulator runs > 1.0×105 times faster on average across various CRB circuits, with a VMID prediction error of only 1.3mV and a delay estimation error as low as 0.6%. The significant speed improvement combined with high accuracy makes our CRB Simulator an efficient and reliable solution for VMID and timing analysis in CRB circuit design.

Long DRAM access latency has a significant impact on modern system performance. However, the improvement of DRAM access latency is limited, as the DRAM vendors reserve considerable timing margins against seldom worst-case conditions. To mitigate such pessimistic timing margins, we propose a temperature- and process-variation-aware timing detection and adaption DRAM (TPDA-DRAM) architecture. It equips in-situ cross-coupled detectors to monitor the voltage difference between bitline pairs, enabling estimation of timing margins caused by process and temperature variations. Moreover, TPDA-DRAM incorporates two collaborative timing adaption schemes: 1) a process-variation-aware timing adaption scheme (PVA) that selectively accelerates the access to weak cells, and 2) a temperature-variation-aware timing adaption scheme (TVA) that precisely adjusts timing parameters by adopting temperature information. Compared to prior art, the proposed detector reduces detection deviation by 54.8% and area overhead by 88.1%. The system-level evaluation in an eight-core system shows that TPDA-DRAM improves the average performance and energy efficiency by 20.5% and 15.0%, respectively.

With the application of low-power design technologies such as dynamic voltage and frequency scaling (DVFS) and globally asynchronous locally synchronization (GALS), a multi-voltage-/frequency-domain network-on-chip (NoC) suffers more and more serious metastability issue in inter-core data communication. To mitigate the metastability during the clock-domain crossing, a technique titled metastability inference and avoidance (MIAA) is presented. MIAA infers the potential metastability risk of a synchronizer's sampling clock through phase detection of a phase-related clock. MIAA avoids the occurrence of metastability by adaptively modulating the clock phase of the sampling clock once it infers the potential metastability risk. We designed a MIAA-based 40nm GALS$2\times 2$NoC that contains four independent voltage/frequency domains. The post-layout simulation results show that MIAA can well predict the metastability risks and reduce the probability of metastability to zero across a wide range of frequency ratios. The metastability mitigation allows us to use a single flip-flop instead of a multi-stage synchronizer for synchronization in the NoC, thereby improving the latency and throughput of the NoC by 40.2% and 79%, respectively.

With the increasing of dynamic random access memory’s (DRAM) capacity, the refresh operation rapidly becomes a major concern to the performance of the current computational system. Moreover, conservative timing parameters adopted for access operations make an increasing amount of negative impact on system performance and energy efficiency. In this article, we propose an in-situ charge detection and adaptive data restoration DRAM (CDAR-DRAM) architecture, which can dynamically adjust the refresh rate and relax the constraints on access timing by removing pessimistic timing margins for PVT variations. CDAR-DRAM employs a low-cost skewed-inverter-based detector to monitor the bitline voltage in runtime and estimate real-time timing parameters of cells. Based on the detector, an adaptive refresh and restore scheme (CDAR-ref) is presented, which progressively reduces the refresh rate and partially restores cells’ voltage just enough for cells with sufficient charge, thereby optimizing both refresh and restoration operations. Moreover, a supplementary adaptive access scheme (CDAR-acc) is presented, which detects the runtime charge level of recently accessed rows and reduces access latency aggressively, benefitting workloads in a single-core system and memory nonintensive workloads in a multicore system. CDAR’s flexibility allows the two schemes to be combined. The evaluation shows that in an eight-core system, the combined scheme improves performance and energy efficiency by 15.2% and 22.6%, respectively.

As the capacity of DRAM continues to grow, the refresh operation rapidly becomes the performance and power-efficiency bottleneck. Also, restore time, the time given for recharging cells post access, makes an increasingly large amount of negative impact on performance. To tackle these problems, in this paper, we propose an in-situ charge detection and adaptive data restoration DRAM (CDAR-DRAM) architecture, which can dynamically adjust the refresh rate and also relax the constraints on restore time. The proposed CDAR-DRAM employs a low-cost skewed-inverter-based detector, which can reduce the excessive timing margins that prior work added to guarantee the functionality of leaky DRAM cells under the worst-case temperature condition. Moreover, an adaptive DRAM refresh and restore scheme is proposed, which can switch automatically between two modes: (i) a refresh mode that supports adaptive refresh rate, and (ii) a restore mode that relaxes the constraints on restore time dynamically for cells having sufficient charge. With the transistor-and architecture-level simulations, we evaluate the CDAR-DRAM in an 8-core system across different workloads. Compared with the prior art, the proposed architecture achieves a 9.4% improvement in system performance and a 14.3% reduction in energy consumption, without requiring the time-consuming profiling process which many prior works employed.