In this paper, a 63–86-GHz receiver (RX) is proposed using a wideband noise-cancelling low noise amplifier (LNA) with phase and amplitude compensation circuit. Such phase and amplitude compensation circuit consists of a 4-to-1 asymmetric power-combining transformer and two amplitude adjusting amplifiers, which improves the noise-cancelling ratio of mm-wave LNA. Meanwhile, a wideband active mixer and an absorptive IF amplifier are introduced to provide a reflectionless operation for signal quality improvement. Based on aforementioned structures, a wideband RX is implemented and fabricated using a conventional 40-nm CMOS technology. The measured results show that the RX achieves 22.5-dB conversion gain with 23-GHz 3-dB bandwidth and 50.7-mW power consumption. The minimum NF is 5.6-dB with less than 1.9-dB variation in the whole operation band.

In this paper, a$\emph{\textbf{W}}$-band$2\times 2$phased-array transmitter with digital gain compensation is proposed to minimize amplitude and angle errors of synthesized beams. The RF phase-shifting architecture is utilized for the phased-array transmitter to reduce circuit blocks and lower system complexity. The high-resolution phase shifting is achieved by a vector-sum phase shifter, which is based on a quadrature-all-pass filter (QAF) with compensation network and Gilbert-type variable gain amplifiers (VGAs) with digital-controlled current digital-to-analog converters (I-DACs). To lower the gain error introduced by the phase shifter in RF phase-shifting architecture, the variable-gain power amplifier (VGPA) is proposed. The gain of the VGPA is finely adjusted to compensate the gain variation of phase shifter in different phase states. Meanwhile, the phase variation of the VGPA under variable gain states is optimized to avoid the influence on phase errors. To verify the aforementioned mechanism, a$\emph{\textbf{W}}$-band$2\times 2$phased-array transmitter is implemented and fabricated in a conventional 40-nm CMOS technology. Based on the digital gain-compensation technique, the phased-array transmitter exhibits a less than 1.12dB RMS gain error and less than 1.82$^\circ$RMS phase error. In addition, the fabricated chip achieves 8.13dBm peak saturated output power and better than 9dB power gain with 135mW power consumption for each channel.

A cascaded mode-switching sub-sampling PLL with quadrature dual-mode voltage waveform-shaping oscillator is proposed in this paper. The dual-mode voltage waveform-shaping oscillator is introduced to extend the tuning range and improve phase noise performance at mm-wave frequency, simultaneously. Meanwhile, the dual-mode quadrature topology is investigated to reduce the phase noise and quadrature phase error, compared to conventional quadrature oscillator. Then, the proposed oscillator is applied in a cascaded PLL with divider-less mode-switching sub-sampling loop, which can obtain the merits of high frequency-resolution, low loop noise, and wide frequency locking range. Both the dual-mode voltage waveform-shaping oscillator and the cascaded PLL are verified and fabricated in a 28-nm CMOS process. The FoM and FoMTof the oscillator at 10 MHz offset are -188.2 dBc/Hz and -200.7 dBc/Hz respectively. The proposed PLL prototype exhibits a frequency range from 22.8 to 33.9 GHz with a typical power consumption of 41.7 mW. The phase noise across the frequency band is from -104.1 to -108.2 dBc/Hz at 1 MHz offset. The jitter FoMjis -236.2 dB.