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Akanksha Yadav

dblp:263/6187 · DBLP profile ↗
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3ranked-venue papers
0as first author
2since 2021 · last 2026
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 2 · 2 since 2021Systems, architecture and hardware · 1Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 87% Integrated circuit design · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
circuit simulation
0.412020
A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Electronic design automation › circuit simulation
mixed-signal simulation
0.412020
A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Integrated circuit design › semiconductor devices
silicon-on-insulator
0.112020
A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020

Methods — techniques the papers use, named apart from their topics

newton-raphson iteration · 0.4interpolation · 0.4
YearPublicationVenuePosition
2026 TransWaveNet: Multi-scale Transformer-Wavelet Fusion for Colorectal Polyp Segmentation
Amit Shakya, Akanksha Yadav, Shruti S. Phutke, Lalit Sharma
ICPR (6)2
2024 MD-DCNN: Multi-Scale Dilation-Based Deep Convolution Neural Network for epilepsy detection using electroencephalogram signals
Karnati Mohan, Geet Sahu, Akanksha Yadav, Ayan Seal, Joanna Jaworek-Korjakowska, Marek Penhaker, Ondrej Krejcar
Knowl. Based Syst.3
2020 A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping
abstract
In this paper, a new look-up table (LUT) method is proposed to reduce the simulation time and the run time memory requirement for large logic and mixed signal simulations. In the proposed method, for the first time, circuit with multiple devices is replaced by one LUT model, called circuit LUT. The replacement results in significant reduction of the run time memory requirement. The replacement also reduces the number of interpolation steps to be performed at every Newton-Raphson iteration during the simulation that results in significant reduction of simulation time. With the proposed method, the simulation speed is improved by two times over the conventional LUT models developed for devices. In addition, 25% reduction in the run time memory requirement is also achieved by the proposed method.
Sitansusekhar Roymohapatra, Ganesh R. Gore, Akanksha Yadav, Mahesh B. Patil, Krishnan S. Rengarajan, Subramanian S. Iyer, Maryam Shojaei Baghini
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3