Root-of-Trust (RoT) uses the hardware primitives to provide security in the integrated electronic systems, preventing attacks against the vital information of the system. The typical hardware primitives are used to generate random numbers and store the system's keys. However, the implementation of these primitives achieves challenges in the system due to the physical phenomena used to obtain the entropy for the random number. On the other hand, the non-volatile memories request special technologies with additional processes and layers. This work presents an implementation of a One-Time Program (OTP) memory using an Anti-Fuse (AF) methodology in 180nm standard CMOS technology. In addition, a Physical Unclonable Function (PUF) is unified, exploiting the post-program current generated in the OTP bit cell. A 128-bit OTP array and high-voltage driver are implemented without any special process and layer, occupying 68000μm2. On the other hand, the PUF implementation achieves 49.02% of uniformity, 49.52% of uniqueness, and 99.88% of reliability in the worst case with Process, Voltage, and Temperature (PVT) variations. In addition, the PUF reports a 2651F2/bit normalized area. The OTP memory application needs 6.7-V to program the AF bit cell.

Hardware security primitives provide Root-of-Trust (RoT) procedures for booting, authentication, and key generation processes in secure integrated systems. The RoT requires True Random Number Generators (TRNGs), Physical Unclonable Functions (PUFs), and non-volatile memories for essential key generation and identity authentication. However, these implementations introduce challenges due to the physical phenomena used in each primitive, requiring complex calibration or special technologies with additional masks. In addition, the integration of separated implementations in a single system-on-a-chip increases the area overhead. This work describes a unified PUF-TRNG in a Non-Volatile Random Access Memory (NVRAM) implementation in 180-nm CMOS technology. The PUF and TRNG primitives are based on the NVRAM metastability in the sense amplifier. The TRNG passes the statistical and entropy tests provided by NIST SP800-22 and SP800-90B, respectively. In addition, the normalized minimum entropy of the TRNG is 0.987 in the worst case with PVT (Process, Voltage, and Temperature) variations. The PUF uniformity, uniqueness and reliability are 49.85%, 48.12% and 99.58%, respectively at nominal conditions. Moreover, the PUF reach$\mathbf{6735} F^{2}/\mathbf{bit}$normalized area11F2= (area)/(minimum feature size of the process)2. The NVRAM needs 8.5V for the programming and erasing modes. Finally, the unified implementation occupies$\mathbf{43155}\mu m^{2}$with$\mathbf{1332}kF^{2}$of normalized area.

This poster presents a Trusted Execution Environment (TEE) hardware implementation based on a heterogeneous architecture. The TEE verifies the integrity of software applications based on a chain of trust with the initial authentication. The chain-of-trust is implemented in software, using TEE hardware crypto-processors. The initial authentication is called the Root-of-Trust (RoT), and the isolated 32-bit system handles it. On the peripheral bus, there are several cryptography accelerators implemented such as SHA- 3, ED25519, AES, and a True Random Number Generator (TRNG). The TRNG module has not only the public channel over the peripheral bus but also a special private channel just for the isolated core. The proposed system was implemented in a 5mm x 5mm die by the 180-nm ROHM process library.