On-chip power planning is a crucial step in chip design. As process nodes advance and the need to supply lower operating voltages without loss becomes vital, the optimal design of the Power Delivery Network (PDN) has become pivotal in VLSI to mitigate IR-drop effectively. To address IR-drop issues in the latest nodes, a back-side power delivery network (BSPDN) has been proposed as an alternative to the conventional front-side PDN. However, BSPDN encounters design issues related to the pitch and resistance of through-silicon vias (TSV s). In addition, BSPDN faces optimization challenges due to the trade-off between rail and grid IR-drop, particularly in the effectiveness of uniform grid design patterns. In this study, we introduce a design framework that utilizes reinforcement learning to identify optimized grid width patterns for individual VLSI designs on the silicon back-side, aiming to reduce IR-drop. We have applied our design approach to various benchmarks and validated its improvement. Our results demonstrate a significant improvement in total IR-drop, with a maximum improvement of up to −19.0% in static analysis and up to −18.8% in dynamic analysis, compared to the conventional uniform BSPDN.

The semiconductor foundries are now mass-producing 3nm transistors. In this trend, many studies on 2nm node report the potential of future transistors such as forksheet FET (FSFET) from the device perspective. However, only a few studies report the impact of advanced transistors at the full-chip level. Thus, this study focuses on enlightening the potential of FSFET at the full-chip level in the 2nm process compared to the 3nm node currently in mass production. To do this, we present FS2K, the first public 2nm technology library in FSFET, which provides the following results: 1) The simple scaling with no variation in devices or interconnect achieves only about 10% power reduction and area reduction in 2nm processes for FSFET and Nanoshet FET (NSFET). 2) An optimal performance improvement in a 2nm node requires FSFET to be designed in a 4T standard cell that is 1-track reduced from 3nm. Our 2nm 4T-FSFET design achieves -29.5% area reduction and -31.9% power reduction compared to the existing 3nm process. Thus, we emphasize the importance of optimization not only in the device but also in the cell layout for future processes.

The imminent rise in data consumption and the physical constraints of current advanced CMOS scaling hasten the end of the projection to the binary system. For a breakthrough of these issues, the ternary system, known for its superior efficiency in expressing numbers (closest to$\mathrm {e}\approx ~2.7183$) has garnered considerable attention. Among the ternary studies reported, the anti-ambipolar transistor (AAT) is acquiring attention thanks to its unique negative differential resistance (NDR) and anti-ambipolar characteristics (AAC). Moreover, easy-to-fabricate inkjet-printing based AAT was introduced. Therefore, in this paper, we propose a practical design methodology (‘$\mathbf {T^{3}L:} $The Tri-transistor Ternary Logic’) and a set of novel ternary logic based on inkjet-printed AATs and CMOSs. In detail, 1) We propose balanced ternary full adders (BTFA) and prove that inkjet-printed AATs and CMOSs are highly capable of implementing any kind of ternary logic. 2) We propose two design methodologies for ternary logic design: NDR-based Design Method I and AAC-based Design Method II. 3) We present optimization methodology for inkjet-printed ternary circuit stability and provide circuitry to secure sufficient noise margin. We provide a highly-compact BTFA design that requires only 64 transistors and an ultra-low-power BTFA design that reduces power by 84.7% to 98.8% compared to the previous designs.

The predicted end of scaling and the exponential increase of user data in the era of the connected world are asking whether the current binary systems in CMOS can successfully provide solutions to the expected challenges. Regarding these challenges, ternary systems are showing a high potential to provide solutions to these known issues. In detail, the tunnelling-based MOSFET (T-CMOS) is reported as promising compared to any other ternary devices studied. However, despite the potential, studies lack how a complete system can be designed in actual T-CMOS-based circuitry. Therefore, in this paper, we provide a holistic study of how T-CMOS-based circuits can be designed. In detail, 1) we provide a pathway to designing a balanced ternary full adder and provide the fundamental of how combinational ternary logic can be designed in T-CMOS. 2) We present various sequential ternary logic based on T-CMOS. 3) We present various circuit techniques that could enhance the performance of combinational and sequential ternary logic. Based on our study, we provide the first balanced ternary adder that the transistor count is only 42 and enhance the operating frequency of the T-CMOS-based ternary system by$5.6\times $to$58.5\times $.

Acoustic-resolution photoacoustic micro-scopy (AR-PAM) is an emerging biomedical imaging modality that combines superior optical sensitivity and fine ultrasonic resolution in an optical quasi-diffusive regime (~1-3 mm in tissues). AR-PAM has been explored for anatomical, functional, and molecular information in biological tissues. Heretofore, AR-PAM systems have suffered from a limited field-of-view (FOV) and/or slow imaging speed, which have precluded them from routine preclinical and clinical applications. Here, we demonstrate an advanced AR-PAM system that overcomes both limitations of previous AR-PAM systems. The new AR-PAM system demonstrates a super wide-field scanning that utilized a 1-axis water-proofing microelectromechanical systems (MEMS) scanner integrated with two linear stepper motor stages. We achieved an extended FOV of $36 \times 80$ mm2by mosaicking multiple volumetric images of $36 \times 2.5$ mm2with a total acquisition time of 224 seconds. For one volumetric data (i.e., $36 \times 2.5$ mm2), the B-scan imaging speed over the short axis (i.e., 2.5 mm) was 83 Hz in humans. The 3D volumetric image was also provided by using MEMS mirror scanning along the X-axis and stepper-motor scanning along the Y-axis. The super-wide FOV mosaic image was realized by registering and merging all individual volumetric images. Finally, we obtained multi-plane whole-body in-vivo PA images of small animals, illustrating distinct multi-layered structures including microvascular networks and internal organs. Importantly, we also visualized microvascular networks in human fingers, palm, and forearm successfully. This advanced MEMS-AR-PAM system could potentially enable hitherto not possible wide preclinical and clinical applications.