Shao-Hong Yang

dblp:264/2730 · DBLP profile ↗
← Back
3ranked-venue papers
1as first author
3since 2021 · last 2024
0000-0003-3204-7391ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author · 3 since 2021
YearPublicationVenuePosition
2024 Highly Reliable PUF Circuits Using Efficient Post-Processing Stabilization Technique
abstract
A Physically Unclonable Function (PUF) circuit is purposefully engineered to leverage the inherent variations in manufacturing processes to generate distinct identities. However, the efficacy of PUFs can be compromised due to the influence of external factors such as noise and environmental variations, which can lead to instability of identities. In this paper, a novel post-processing stabilization technique is introduced, utilizing a mismatch recombination algorithm and resulting in a 31× reduction of the Bit Error Rate (BER) to 0.19%. Through the application of this stabilization technique in conjunction with a modified self-compared Ring Oscillator (RO) architecture, the proposed PUF achieves a uniqueness of 49.96%. Moreover, the proposed PUF exhibits substantial resilience against temperature variations, maintaining a BER of under 2% across the temperature range from 0°C to 45°C. The proposed PUF was implemented and verified on a Xilinx Artix-7 FPGA.
Yu-Hsiang Tseng, Shao-Hong Yang, Tsung-Te Liu
ISCAS2
2023 A Highly Stable Physically Unclonable Function Using Algorithm-Based Mismatch Hardening Technique in 28-nm CMOS
abstract
Physically unclonable function (PUF) is an emerging security solution for Internet of Things (IoT) devices. However, PUF faces a critical design challenge: responses should remain the same regardless of environmental conditions. This article presents an algorithm-based mismatch hardening technique that provides an effective and efficient solution to stabilizing PUF responses, which could be applied to various PUF circuits. The proposed stabilization technique combines multiple mismatches to achieve high reliability with minimum loss of utility. Moreover, the proposed approach requires only the available digitized PUF responses, avoiding any auxiliary measurement circuit to minimize additional implementation and testing overhead. The PUF test chip implemented in 28-nm CMOS technology shows that the proposed stabilization technique achieves a highly stable performance, lowering the nominal bit error rate (BER) to 0.0016%. It also exhibits excellent reliability with a worst-case BER of 0.16% across 0.7 to 1.2 V and −50 to 125°C, proving to be a promising candidate for security primitive for IoT applications.
Shao-Hong Yang, Tsung-Te Liu
IEEE Trans. Circuits Syst. I Regul. Pap.1
2022 A Robust Area-Efficient Physically Unclonable Function With High Machine Learning Attack Resilience in 28-nm CMOS
abstract
Strong physically unclonable function (PUF) offers a promising solution to low-cost hardware identification and authentication for Internet of Things (IoT) applications. The continuous advancement of machine learning (ML) technology makes the PUF resilience to ML attacks a major design priority. This paper presents a robust and area-efficient strong PUF design with high ML attack resilience. The proposed PUF architecture based on inverter amplifiers operating in the subthreshold region achieves both low energy consumption and high supply and temperature scalability. The proposed nonlinearity topology effectively enhances PUF resilience to various ML attacks with low implementation area and cost. The proposed strong PUF design was designed and implemented using a 28-nm CMOS process. The measurement results show that the proposed PUF design achieves a nearly ideal ML attack resilience of 49.96 % with a small area of 239,857 F2, and demonstrates a stable operation across a wide range of supply voltage from 0.5–1.4 V and temperature from −40–100 °C. This represents$3\times $improvement in area efficiency,$2.25\times $and$1.08\times $improvement in operating voltage and temperature range, respectively, compared to the state-of-the-art results.
You-Cheng Lai, Chun-Yen Yao, Shao-Hong Yang, Ying-Wei Wu, Tsung-Te Liu
IEEE Trans. Circuits Syst. I Regul. Pap.3