Marginal defects, such as high-resistance short or low-resistance open defects, are hard to detect by conventional pass-fail test methods because their manifestations are practically indistinguishable from the effects of regular variations. However, their coverage is essential for circuits with high-quality requirements and/or when early-life failures are a concern. In this paper, we propose an alternative detection concept based on evaluating several parametric responses of a circuit against a machine learning (ML) model. We use a 14nm FinFET transistor model validated against industrial measurements. We show that high detection performance is possible even when unsupervised learning that does not consider defective behavior is used; to this end, the procedure is generic. Moreover, an AUC score of over 0.96 is achieved when only measurements from a single voltage level are utilized, in contrast to earlier work. We also present a procedure to select a reduced set of test sequences, achieving an improvement of 50% reduction with a limited impact on detection performance.

Large datasets are often available for machine learning tasks. However, only very few contain labels for all the samples because labeling is a very labor-intensive process. Hence, large unlabeled datasets are available but inaccessible to traditional supervised learning methods. In this work, we combine two approaches to reduce the number of required labels. First, self-supervised learning (SSL) to utilize the large unlabeled dataset. SSL creates an encoder from those unlabeled samples that transforms the input into intermediate feature representations. Second, active learning is employed for the classification where labels are required. Active learning intelligently selects the most informative samples for manual labeling. Thus, it reduces the amount the labels required to achieve a high classification accuracy. The selected samples are used to train a brain-inspired hyperdimensional computing and random forest classifier. We demonstrate the outstanding performance of our approach with the example of wafer map defect pattern classification. It is a crucial diagnostic task helping to identify systematic problems in the manufacturing and improving yield. With our proposed method, a high 97% classification accuracy is achieved with only 6% of the labeled dataset for the first time. Our approach demonstrates the potential for training a machine learning model from less labeled samples by combining SSL with active learning.

The pivotal issue of reliability is one of the major concerns for circuit designers. The driving force is transistor aging, dependent on operating voltage and workload. At the design time, it is difficult to estimate close-to-the-edge guardbands that keep aging effects during the lifetime at bay. This is because the foundry does not share its calibrated physics-based models, comprised of highly confidential technology and material parameters. However, the unmonitored yet necessary overestimation of degradation amounts to a performance decline, which could be preventable. Furthermore, these physics-based models are computationally complex. The costs of modeling millions of individual transistors at design time can be exorbitant. We propose the use of a machine learning model trained to replicate the physics-based model, such that no confidential parameters are disclosed. This effectual workaround is fully accessible to circuit designers for the purposes of design optimization. We demonstrate the model’s ability to generalize by training on data from one circuit and applying it successfully to a benchmark circuit. The mean relative error is as low as 1.7%, with a speedup of up to$20\times $. Circuit designers, for the first time ever, will have ease of access to a high-precision aging model, which is paramount for efficient designs. In contrast to existing work, our approach takes the full switching activity into account to model recovery effects. This work is a promising step in the direction of bridging the gap between the foundry and circuit designers.