The advent of quantum computing has engendered a widespread proliferation of efforts utilizing qubits for optimizing classical computational algorithms. Number Theoretic Transform (NTT) is one such popular algorithm that accelerates polynomial multiplication significantly and is consequently, the core arithmetic operation in most homomorphic encryption algorithms. Hence, fast and efficient execution of NTT is highly imperative for practical implementation of homomorphic encryption schemes in different computing paradigms. In this paper, we, for the first time, propose an efficient and scalable Quantum Number Theoretic Transform (QNTT) circuit using quantum gates. We introduce a novel exponential unit for modular exponential operation, which furnishes an algorithmic complexity of O(n). Our proposed methodology performs further optimization and logic synthesis of QNTT, that is significantly fast and facilitates efficient implementations on IBM’s quantum computers. The optimized QNTT achieves a gate-level complexity reduction from power of two to one with respect to bit length. Our methodology utilizes 44.2% fewer gates, thereby minimizing the circuit depth and a corresponding reduction in overhead and error probability, for a 4-point QNTT compared to its unoptimized counterpart.

The exponential proliferation of Malware over the past decade has threatened system security across a plethora of Internet of Things (IoT) devices. Furthermore, the improvements in computer architectures to include speculative branching and out-of-order executions have engendered new opportunities for adversaries to carry out microarchitectural attacks in these devices. Both Malware and microarchitectural attacks are imperative threats to computing systems, as their behaviors range from stealing sensitive data to total system failure. With the cat-and-mouse game between Anti-Virus Software (AVS) and attackers, the frequent bolstering of AVS induces large computational overhead. Consequently, hardware performance counter (HPC)-based detection strategies augmented with machine learning (ML) classifiers have gained popularity as a low overhead solution in identifying these malicious threats. However, ML models are operated as black boxes, which results in decisions that are not human understandable. Clarity of the models’ results facilitates the development of more robust systems. Existing explainable frameworks are only capable of determining each feature’s impact on a prediction which does not provide meaningful interpretable outcomes for HPC-based intrusion detection. In this article, we address this issue by proposing an explainable HPC-based double regression (HPCDR) ML framework. Our proposed technique provides relevant transparency through isolation of the most malevolent transient window of an application, thereby allowing a user to efficiently locate the pernicious instructions within the program. We evaluated HPCDR on five microarchitectural attacks and two Malware. HPCDR was successfully able to identify the most malicious function manifested in each intrusive application.

Prevention of integrated circuit counterfeiting through logic locking faces the fundamental challenge of securing an obfuscation key against both physical and algorithmic threats. Previous work has focused on strengthening the logic encryption to protect the key against algorithmic attacks, but failed to provide adequate physical security. In this work, we propose a logic locking scheme that leverages the non-volatility of the nanomagnet logic (NML) family to achieve both physical and algorithmic security. Polymorphic NML minority gates protect the obfuscation key against algorithmic attacks, while a strain-inducing shield surrounding the nanomagnets provides physical security via a self-destruction mechanism.

In the age of Internet-of-Things (IoT), automobiles have become heavily integrated and reliant on computerized components for system functionality. Modern vehicles have many Electronic Control Units (ECUs) that control ignition timing, suspension control, and transmission shifting. The Engine Control Module (ECM) is generally recognized as one of the most essential components owing to its functionality of regulating air and fuel input to the engine. Consequently, automotive security is an emerging problem that will only escalate as vehicles integrate more computerized components in conjunction with wireless system connectivity. Attackers that successfully gain access to important vehicular components and compromise existing functionality can induce a plethora of malevolent activities. With the evolution and exponential proliferation of Malware, identifying malicious entities is critical for maintaining proper system performance. Traditional anti-virus software is inadequate against complex Malware, which has engendered a push towards Hardware-assisted Malware Detection (HMDs) using Hardware Performance Counters (HPCs). HPCs are special purpose registers that track low-level micro-architectural events. In this paper, we propose using Machine Learning models trained on HPC data to identify malicious entities in the ECM. Our experimental results determine that the proposed ML-based models can successfully identify malicious actions in an automotive system with a classification accuracy of up to 96.7%.

In the era of Internet of Things (IoT), Malware has been proliferating exponentially over the past decade. Traditional anti-virus software are ineffective against modern complex Malware. In order to address this challenge, researchers have proposed hardware-assisted Malware detection (HMD) using hardware performance counters (HPCs). The HPCs are used to train a set of machine learning (ML) classifiers, which in turn, are used to distinguish benign programs from Malware. Recently, adversarial attacks have been designed by introducing perturbations in the HPC traces using an adversarial sample predictor to misclassify a program for specific HPCs. These attacks are designed with the basic assumption that the attacker is aware of the HPCs being used to detect Malware. Since modern processors consist of hundreds of HPCs, restricting to only a few of them for Malware detection aids the attacker. In this article, we propose a moving target defense (MTD) for this adversarial attack by designing multiple ML classifiers trained on different sets of HPCs. The MTD randomly selects a classifier; thus, confusing the attacker about the HPCs or the number of classifiers applied. We have developed an analytical model which proves that the probability of an attacker to guess the perfect HPC-classifier combination for MTD is extremely low (in the range of $10^{-1864}$ for a system with 20 HPCs). Our experimental results prove that the proposed defense is able to improve the classification accuracy of HPC traces that have been modified through an adversarial sample generator by up to 31.5%, for a near perfect (99.4%) restoration of the original accuracy.

Micro-architectural footprints can be used to distinguish one application from another. Most modern processors feature hardware performance counters to monitor the various micro-architectural events when an application is executing. These ready-made hardware performance counters can be used to create program fingerprints and have been shown to successfully differentiate between individual applications. In this paper, we demonstrate how ready-made hardware performance counters, due to their coarse-grain nature (low sampling rate and bundling of similar events, e.g., number of instructions instead of number of add instructions), are insufficient to this end. This observation motivates exploration of tailor-made hardware performance counters to capture fine-grain characteristics of the programs. As a case study, we evaluate both ready-made and tailor-made hardware performance counters using post-quantum cryptographic key encapsulation mechanism implementations. Machine learning models trained on tailor-made hardwareperformance counter streams demonstrate that they can uniquely identify the behavior of every post-quantum cryptographic key encapsulation mechanism algorithm with at least 98.99% accuracy.

Transient execution attacks exploit performance optimizations, built into modern CPU designs, to leak sensitive data through side channels. Preventing such attacks is limited: (1) Software solutions engender high performance overhead, and (2) Hardware solutions require new CPU designs and intensive formal analysis, which is impractical due to the tremendous complexity of modern CPUs and lack of public documentation. To address these challenges, Hardware-Malware Detectors (HMDs), which utilize Hardware Performance Counters (HPCs), have been proposed to detect transient execution attacks as a computational anomaly, with a low impact on performance. Unfortunately, some recent studies show that HMDs detection can be easily evaded by obfuscating the HPC traces. Upon observing that two main methods mostly generate evasive transient execution attacks, namely gradient-based and sleep based, in this paper, we propose nondifferentiable HMDs (ND-HMDs) to defend against evasive transient execution attacks. In particular, ND-HMDs use nondifferentiable, gradient-free classifiers, rendering the gradient computations on ND-HMDs less useful for generating evasion samples. Our extensive evaluation shows that ND-HMDs can successfully defend against the gradient-based attacks, and are quite resistant to sleep based attack; while at the same time, ND-HMDs achieve high detection accuracy on the non-evasive transient execution attacks.