This work presents a new analog-to-digital converter (ADC) architecture named programmable converter array (PCA) for multi-standard signal acquisition. Unlike prior reconfigurable ADCs that are mainly configured at the circuit level, PCA is highly flexible at the architecture level and can process multiple input signals simultaneously for mode concurrency. The elemental units in the converter array are Conversion Blocks (CBs) based on successive approximation register (SAR) ADCs. Multiple CBs can interleave or run synergically through a bus system to form sophisticated architectures. Fabricated in 28nm CMOS, the prototype converter array can be configured as over 16 modes, with an SNDR range from 30dB to 82dB and an aggregate bandwidth from sub-MHz to 1000MHz. The prototype achieves a peak Schreier figure of merit (FoMs) of 176dB while maintaining FoMs over 165dB in most configurations, and occupies only 0.1mm2 of silicon area.

This work proposes a dithered-digital-mixing background timing-skew calibration method for time-interleaved (TI) analog-to-digital converters (ADCs). Unlike prior digital-mixing methods that limit the input bandwidth or lead the calibration process to a limit cycle, the proposed method enhances the input bandwidth to the Nyquist frequency and guarantees the convergence. This is achieved by a pseudo-random binary sequence generator that produces a dither signal. Practical considerations including thermal noise and the step size of variable delay lines are discussed. Behavioral simulation results demonstrate the effectiveness of the proposed method with an improvement of signal-to-noise-and-distortion ratio from 26.3dB to 52.6dB for a 5GS/s 9b 16-channel TI ADC.

High-speed time-interleaved analog-to-digital converters (TI-ADCs) are sensitive to timing skew mismatch. Autocorrelation-based background timing skew calibration techniques require small hardware overhead as they rely on the TI-ADC input signal for calibration. However, such techniques suffer from a very long convergence time. This paper proposes a new correlation-based technique that boosts convergence speed by orders of magnitude compared to existing autocorrelation-based techniques. The technique uses a digital window detector and calculates the signal correlation funnction around zero-crossings only. Practical design considerations including thermal noise, clock jitter, quantization and offset mismatch are discussed. Behavioral simulation results for two TI-ADCs with different speeds, resolutions and interleaving factors are presented.